800GE Dual Interface Model-M

800GE port speeds bring better economies of scale, higher bandwidth for increased network traffic throughput without increasing footprint. This facilitates the deployment of high port count 800GE network equipment. At these high rates, the high-speed serial paths must be carefully tuned and tested for the best signal integrity, lower BERs, reliable long duration FEC Symbol Error Correction performance, and diverse interoperability requirements.

Challenge: Characterize network device interoperability and performance before deployment in a 800GE-capable production network

The need for more bandwidth is being driven by the unrelenting demand for greater bandwidth, lower cost per gigabit of traffic, and lower power consumption of network devices, and no increase in data center footprint. Devices that support up to 106Gb/s electrical lane signaling, PAM4 encoding, and RS (544,514) Forward Error Correction double the Ethernet gigabits per second by allowing 800Gb/s throughput in the same form factor and with the same power as required for 400Gb/s per second.

High-speed serial communications links are transitioning from 400GE over 53 Gb/s lanes to the faster 106 Gb/s lanes. A 53Gb/s serializer/deserialize (SerDes) PHY can support 1x400GE, 2x200GE, 4x100GE, and 8x50GE speeds per port. A 106Gb/s SerDes maintains the number of electrical lanes as 400GE, and doubles the speed per lane compared to 400GE. It doubles the Ethernet speed support on a per-port basis to: 2x400GE, 4x200GE and 8x100GE, and 1x800GE.

Additionally, there has emerged two dominate form factors for high-speed network equipment interconnects: QSFP-DD800 and OSFP800. These pluggable interconnects have many different configurations in their optical wavelengths, electrical lane speeds, and support for one or more Ethernet speeds. This creates a high demand for interoperability testing.