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Training at a Glance

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Format

  • Classroom training

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Audience

  • Developers of SoC components
  • Evaluators of SoC components

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Duration

  • 6 courses
  • 4 days
  • 32 hours

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Outcomes

  • Get a holistic view of chip security
  • Understand how chip security affects designing, implementing, and testing SoC components or platforms

Ensure Cybersecurity in the SoC Design Process

This course is aimed at developers and evaluators of system-on-chip (SoC) components, with an emphasis on hardware design. Developers will broaden their view of the complete development process while evaluators gain insight into how it is followed. The goal of the training is to provide a holistic view for both developers and evaluators, enabling them to interact more and work together effectively for increased security.

Prerequisites

  • Experience with HDL languages and familiarity with HDL terminology
  • Awareness of fundamentals for physical CMOS circuit designs and layouts
  • Awareness of basic electronic engineering tooling and concepts

Training Outline

Learn the basics of threat analysis and security terminology needed to enable a solid security foundation in the system. Understand the relevance of a realistic threat model and a rigorous risk assessment.

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Interested in this service? Reach out to learn more.

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