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Training at a Glance

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Format

  • Classroom training

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Audience

  • Developers of SoC components
  • Evaluators of SoC components

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Duration

  • 6 courses
  • 4 days
  • 32 hours

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Outcomes

  • Get a holistic view of chip security
  • Understand how chip security affects designing, implementing, and testing SoC components or platforms

Ensure Cybersecurity in the SoC Design Process

This course is aimed at developers and evaluators of system-on-chip (SoC) components, with an emphasis on hardware design. Developers will broaden their view of the complete development process while evaluators gain insight into how it is followed. The goal of the training is to provide a holistic view for both developers and evaluators, enabling them to interact more and work together effectively for increased security.

Prerequisites

  • Experience with HDL languages and familiarity with HDL terminology
  • Awareness of fundamentals for physical CMOS circuit designs and layouts
  • Awareness of basic electronic engineering tooling and concepts

Training Outline

Learn the basics of threat analysis and security terminology needed to enable a solid security foundation in the system. Understand the relevance of a realistic threat model and a rigorous risk assessment.

Learn about the physical implementation of SoC security components. We’ll cover security components, interfaces, crypto engines, and algorithms in an SoC. Dig deeper into the implementation of the components down to the physical transistor level. This level of detail is necessary to understand modern attack techniques.

Add security properties to SoCs at several levels by learning best practices (and challenges) for reaching a secure RTL code, secure SoC / component layout, and secure low-level code development (e.g. boot ROM code).

Dive deeper into the challenges that appear when using modern, state-of-the-art SoC technologies. We discuss challenges on the current technology nodes found in an SoC and describe challenges found with integrated Secure Elements (iSE) in the context of SoCs.

In this chapter, gain further insight into the current tooling for attacks on SoCs, the state of current academic research activities, and known attacks. Learn how to rate the attack complexity according to the JIL rating scheme, which is widely used in SoC evaluations.

Understand the methodology under which an evaluation is carried out (focusing on vulnerability discovery, attacks and mitigations, and the threat landscape) and the secure development lifecycle and its relevance for a secure SoC. Finally, learn about some practical aspects of a secure SoC evaluation, such as the situation where different security countermeasures combine in a SoC and aligning planning and development of upcoming chips. This final section is targeted at evaluators and analysts.

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