!!!!    6    0    1  991760712  Vc5a2                                         

! Device           : 74ls595
! Function         : 8 bit shift register with output latches
! revision         : B.01.00
! safeguard        : high_out_lsttl
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

! warning "Pullups required to test high impedance output (pin 15)"

sequential

vector cycle  1u
receive delay 900n

assign   VCC         to pins  16
assign   GND         to pins  8

assign   Gbar        to pins  13
assign   RCK         to pins  12
assign   SCLRbar     to pins  10
assign   SCK         to pins  11
assign   SER         to pins  14

assign   Qh_Qa       to pins  7,6,5,4,3,2,1,15
assign   Qh_Qa0      to pins  15           !AT Added for minimum pin test.
assign   Qh_Qa1      to pins   1           !AT Added for minimum pin test.
assign   Qh_Qa2      to pins   2           !AT Added for minimum pin test.
assign   Qh_Qa3      to pins   3           !AT Added for minimum pin test.
assign   Qh_Qa4      to pins   4           !AT Added for minimum pin test.
assign   Qh_Qa5      to pins   5           !AT Added for minimum pin test.
assign   Qh_Qa6      to pins   6           !AT Added for minimum pin test.
assign   Qh_Qa7      to pins   7           !AT Added for minimum pin test.

assign   Qh9         to pins  9

family   TTL

power    VCC,GND

inputs   Gbar, RCK, SCLRbar, SCK, SER

outputs  Qh_Qa, Qh9
outputs  Qh_Qa0, Qh_Qa1, Qh_Qa2, Qh_Qa3  !AT Added for minimum pin test.
outputs  Qh_Qa4, Qh_Qa5, Qh_Qa6, Qh_Qa7  !AT Added for minimum pin test.

set load on pins 15      to pull up

when Gbar is "1" inactive Qh_Qa

trace Qh_Qa, Qh9 to Gbar, RCK, SCLRbar, SCK, SER

disable        Qh_Qa    with  Gbar to "1"

!***************************************************************
!***************************************************************

vector  Reset
   set   Gbar     to "0"
   set   RCK      to "0"
   set   SCLRbar  to "0"
   set   SCK      to "0"
   set   SER      to "0"
end vector

vector  Keep_Control
   set   Gbar     to "k"
   set   RCK      to "k"
   set   SCLRbar  to "k"
   set   SCK      to "k"
   set   SER      to "k"
end vector

vector  Gbar_high
   initialize     to Keep_Control
   set   Gbar     to "1"
end vector

vector  Clock
   initialize     to Keep_Control
   set   RCK      to "t"
   set   SCK      to "t"
end vector

vector  SER_high
   initialize     to Keep_Control
   set   SER      to "1"
end vector

vector  SER_low
   initialize     to Keep_Control
   set   SER      to "0"
end vector

vector  SCLRbar_high
   initialize     to Keep_Control
   set   SCLRbar  to "1"
end vector

vector  SCLRbar_low
   initialize     to Keep_Control
   set   SCLRbar  to "0"
end vector

vector  Qh_Qa_00000001
   initialize     to Keep_Control
   set   Qh_Qa    to "00000001"
end vector

vector  Qh_Qa_00000010
   initialize     to Keep_Control
   set   Qh_Qa    to "00000010"
end vector

vector  Qh_Qa_00000100
   initialize     to Keep_Control
   set   Qh_Qa    to "00000100"
end vector

vector  Qh_Qa_00001000
   initialize     to Keep_Control
   set   Qh_Qa    to "00001000"
end vector

vector  Qh_Qa_00010000
   initialize     to Keep_Control
   set   Qh_Qa    to "00010000"
end vector

vector  Qh_Qa_00100000
   initialize     to Keep_Control
   set   Qh_Qa    to "00100000"
end vector

vector  Qh_Qa_01000000
   initialize     to Keep_Control
   set   Qh_Qa    to "01000000"
end vector

vector  Qh_Qa_10000000
   initialize     to Keep_Control
   set   Qh_Qa    to "10000000"
end vector

vector  Qh_Qa_00000000
   initialize     to Keep_Control
   set   Qh_Qa    to "00000000"
end vector

vector  Qh_Qa_11111111
   initialize     to Keep_Control
   set   Qh_Qa    to "11111111"
end vector

vector  Qh_Qa_XXXXXXX1
   initialize     to Keep_Control
   set   Qh_Qa    to "XXXXXXX1"
end vector

vector  Qh9_high
   initialize     to Keep_Control
   set   Qh9      to "1"
end vector

vector  Qh9_low
   initialize     to Keep_Control
   set   Qh9      to "0"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector  Qh_Qa0_0
   initialize     to Keep_Control
   set   Qh_Qa0   to "0"
end vector

vector  Qh_Qa0_1
   initialize     to Keep_Control
   set   Qh_Qa0   to "1"
end vector

vector  Qh_Qa1_0
   initialize     to Keep_Control
   set   Qh_Qa1   to "0"
end vector

vector  Qh_Qa1_1
   initialize     to Keep_Control
   set   Qh_Qa1   to "1"
end vector

vector  Qh_Qa2_0
   initialize     to Keep_Control
   set   Qh_Qa2   to "0"
end vector

vector  Qh_Qa2_1
   initialize     to Keep_Control
   set   Qh_Qa2   to "1"
end vector

vector  Qh_Qa3_0
   initialize     to Keep_Control
   set   Qh_Qa3   to "0"
end vector

vector  Qh_Qa3_1
   initialize     to Keep_Control
   set   Qh_Qa3   to "1"
end vector

vector  Qh_Qa4_0
   initialize     to Keep_Control
   set   Qh_Qa4   to "0"
end vector

vector  Qh_Qa4_1
   initialize     to Keep_Control
   set   Qh_Qa4   to "1"
end vector

vector  Qh_Qa5_0
   initialize     to Keep_Control
   set   Qh_Qa5   to "0"
end vector

vector  Qh_Qa5_1
   initialize     to Keep_Control
   set   Qh_Qa5   to "1"
end vector

vector  Qh_Qa6_0
   initialize     to Keep_Control
   set   Qh_Qa6   to "0"
end vector

vector  Qh_Qa6_1
   initialize     to Keep_Control
   set   Qh_Qa6   to "1"
end vector

vector  Qh_Qa7_0
   initialize     to Keep_Control
   set   Qh_Qa7   to "0"
end vector

vector  Qh_Qa7_1
   initialize     to Keep_Control
   set   Qh_Qa7   to "1"
end vector

!***************************************************************
!***************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with Qh_Qa0.

unit "awaretest Qh_Qa0 Test"
   execute  Reset
   execute  SCLRbar_high
   execute  Clock
   execute  Clock
   execute  Qh_Qa0_0

   execute  SER_high
   execute  Clock
   execute  Clock

   execute  SER_low
   execute  Clock
   execute  Clock

   execute  Qh_Qa0_1
end unit

unit "awaretest Qh_Qa1 Test"
   execute  Reset
   execute  SCLRbar_high
   execute  Clock
   execute  Clock
   execute  Qh_Qa1_0

   execute  SER_high
   execute  Clock
   execute  Clock

   execute  SER_low
   execute  Clock
   execute  Clock

   execute  Clock
   execute  Clock
   execute  Qh_Qa1_1
end unit

unit "awaretest Qh_Qa2 Test"
   execute  Reset
   execute  SCLRbar_high
   execute  Clock
   execute  Clock
   execute  Qh_Qa2_0

   execute  SER_high
   execute  Clock
   execute  Clock

   execute  SER_low
   execute  Clock
   execute  Clock

   execute  Clock
   execute  Clock

   execute  Clock
   execute  Clock
   execute  Qh_Qa2_1
end unit

unit "awaretest Qh_Qa3 Test"
   execute  Reset
   execute  SCLRbar_high
   execute  Clock
   execute  Clock
   execute  Qh_Qa3_0

   execute  SER_high
   execute  Clock
   execute  Clock

   execute  SER_low
   execute  Clock
   execute  Clock

   execute  Clock
   execute  Clock

   execute  Clock
   execute  Clock

   execute  Clock
   execute  Clock
   execute  Qh_Qa3_1
end unit

unit "awaretest Qh_Qa4 Test"
   execute  Reset
   execute  SCLRbar_high
   execute  Clock
   execute  Clock
   execute  Qh_Qa4_0

   execute  SER_high
   execute  Clock
   execute  Clock

   execute  SER_low
   execute  Clock
   execute  Clock

   execute  Clock
   execute  Clock

   execute  Clock
   execute  Clock

   execute  Clock
   execute  Clock

   execute  Clock
   execute  Clock
   execute  Qh_Qa4_1
end unit

unit "awaretest Qh_Qa5 Test"
   execute  Reset
   execute  SCLRbar_high
   execute  Clock
   execute  Clock
   execute  Qh_Qa5_0

   execute  SER_high
   execute  Clock
   execute  Clock

   execute  SER_low
   execute  Clock
   execute  Clock

   execute  Clock
   execute  Clock

   execute  Clock
   execute  Clock

   execute  Clock
   execute  Clock

   execute  Clock
   execute  Clock

   execute  Clock
   execute  Clock
   execute  Qh_Qa5_1
end unit

unit "awaretest Qh_Qa6 Test"
   execute  Reset
   execute  SCLRbar_high
   execute  Clock
   execute  Clock
   execute  Qh_Qa6_0

   execute  SER_high
   execute  Clock
   execute  Clock

   execute  SER_low
   execute  Clock
   execute  Clock

   execute  Clock
   execute  Clock

   execute  Clock
   execute  Clock

   execute  Clock
   execute  Clock

   execute  Clock
   execute  Clock

   execute  Clock
   execute  Clock

   execute  Clock
   execute  Clock
   execute  Qh_Qa6_1
end unit

unit "awaretest Qh_Qa7 Test"
   execute  Reset
   execute  SCLRbar_high
   execute  Clock
   execute  Clock
   execute  Qh_Qa7_0

   execute  SER_high
   execute  Clock
   execute  Clock

   execute  SER_low
   execute  Clock
   execute  Clock

   execute  Clock
   execute  Clock

   execute  Clock
   execute  Clock

   execute  Clock
   execute  Clock

   execute  Clock
   execute  Clock

   execute  Clock
   execute  Clock

   execute  Clock
   execute  Clock

   execute  Clock
   execute  Clock
   execute  Qh_Qa7_1
end unit


unit  "test1"
   execute  Reset
   execute  SCLRbar_high
   execute  Clock
   execute  Clock
   execute  Qh_Qa_00000000

   execute  SER_high
   execute  Clock
   execute  Clock

   execute  SER_low
   execute  Clock
   execute  Clock

   execute  Qh_Qa_00000001
   execute  Qh9_low

   execute  Clock
   execute  Clock
   execute  Qh_Qa_00000010

   execute  Clock
   execute  Clock
   execute  Qh_Qa_00000100

   execute  Clock
   execute  Clock
   execute  Qh_Qa_00001000

   execute  Clock
   execute  Clock
   execute  Qh_Qa_00010000

   execute  Clock
   execute  Clock
   execute  Qh_Qa_00100000

   execute  Clock
   execute  Clock
   execute  Qh_Qa_01000000
   execute  Qh9_high

   execute  Clock
   execute  Clock
   execute  Qh_Qa_10000000

   execute  SCLRbar_low
   execute  Clock
   execute  Clock
   execute  Qh_Qa_00000000
end unit

unit  "Enable (Gbar) test"
   execute  Reset
   execute  SCLRbar_high
   execute  Clock
   execute  Clock
   execute  Qh_Qa_00000000

   execute  Gbar_high
   execute  Qh_Qa_XXXXXXX1
end unit

!End of test