!!!!    6    0    1  991700803  V81e0                                         

! Device           : 74ls673
! Function         : 16-bit Shift Registers
! revision         : B.01.00
! safeguard        : standard_lsttl
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

sequential

vector cycle  500n
receive delay 400n

assign   VCC         to pins  28
assign   GND         to pins  14

assign   Y15_Y8      to pins  27,26,25,24,23,21,20,19
assign   Y8          to pins  19          !AT Added for minimum pin test.
assign   Y9          to pins  20          !AT Added for minimum pin test.
assign   Y10         to pins  21          !AT Added for minimum pin test.
assign   Y11         to pins  23          !AT Added for minimum pin test.
assign   Y12         to pins  24          !AT Added for minimum pin test.
assign   Y13         to pins  25          !AT Added for minimum pin test.
assign   Y14         to pins  26          !AT Added for minimum pin test.
assign   Y15         to pins  27          !AT Added for minimum pin test.

assign   Y7_Y0       to pins  18,17,16,13,12,11,10,9
assign   Y0          to pins   9          !AT Added for minimum pin test.
assign   Y1          to pins  10          !AT Added for minimum pin test.
assign   Y2          to pins  11          !AT Added for minimum pin test.
assign   Y3          to pins  12          !AT Added for minimum pin test.
assign   Y4          to pins  13          !AT Added for minimum pin test.
assign   Y5          to pins  16          !AT Added for minimum pin test.
assign   Y6          to pins  17          !AT Added for minimum pin test.
assign   Y7          to pins  18          !AT Added for minimum pin test.

assign   SER_Q15     to pins  7
assign   MODE_STRCLK to pins  6
assign   STRCLRbar   to pins  5
assign   R_Wbar      to pins  4
assign   SH_CLK      to pins  3
assign   CSbar       to pins  2

assign   NC          to pins  1,8,15,22

nondigital   NC

family    TTL

power          VCC,GND

inputs         MODE_STRCLK, STRCLRbar, R_Wbar, SH_CLK, CSbar

outputs        Y15_Y8, Y7_Y0
outputs  Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7          !AT Added for minimum pin test.
outputs  Y8, Y9, Y10, Y11, Y12, Y13, Y14, Y15    !AT Added for minimum pin test.

bidirectional  SER_Q15

disable        SER_Q15 with  CSbar to "1"
disable        SER_Q15 with  R_Wbar to "0"

when CSbar is "1" inactive SER_Q15
when R_Wbar is "1" outputs SER_Q15
when R_Wbar is "0" inputs SER_Q15

trace Y15_Y8, Y7_Y0, SER_Q15 to MODE_STRCLK, STRCLRbar, R_Wbar, SH_CLK, CSbar
trace Y15_Y8, Y7_Y0 to SER_Q15
!***************************************************************
!***************************************************************

vector   Reset
         set   CSbar       to "0"
         set   MODE_STRCLK to "0"
         set   R_Wbar      to "0"
         set   SH_CLK      to "0"
         set   STRCLRbar   to "1"
end vector

vector   Keep_Control
         set   CSbar       to "k"
         set   MODE_STRCLK to "k"
         set   R_Wbar      to "k"
         set   SH_CLK      to "k"
         set   STRCLRbar   to "k"
end vector

vector   Clear_Latch
         initialize to Keep_Control
         set   STRCLRbar   to "0"
end vector

vector   Clock_Latch
         initialize to Keep_Control
         set   MODE_STRCLK to "t"
end vector

vector   Clock_Shift_Register
         initialize to Keep_Control
         set   SH_CLK      to "t"
end vector

vector   Clock_Shift_Register_Serial_Data
         initialize to Keep_Control
         drive SER_Q15
         set   SER_Q15     to "k"
         set   SH_CLK      to "t"
end vector

vector   CSbar_high
         initialize to Keep_Control
         set   CSbar       to "1"
end vector

vector   Data_out_00
         initialize to Keep_Control
         set   Y15_Y8      to "00000000"
         set   Y7_Y0       to "00000000"
end vector

vector   Data_out_55
         initialize to Keep_Control
         set   Y15_Y8      to "01010101"
         set   Y7_Y0       to "01010101"
end vector

vector   Data_out_AA
         initialize to Keep_Control
         set   Y15_Y8      to "10101010"
         set   Y7_Y0       to "10101010"
end vector

vector   Mode_high
         initialize to Keep_Control
         set   MODE_STRCLK to "1"
end vector

vector   Mode_low
         initialize to Keep_Control
         set   MODE_STRCLK to "0"
end vector

vector   Q15_high
         initialize to Keep_Control
         receive SER_Q15
         set   SER_Q15     to "1"
end vector

vector   Q15_low
         initialize to Keep_Control
         receive SER_Q15
         set   SER_Q15     to "0"
end vector

vector   Read
         initialize to Keep_Control
         set   R_Wbar      to "1"
end vector

vector   Serial_in_high
         initialize to Keep_Control
         drive SER_Q15
         set   SER_Q15     to "1"
end vector

vector   Serial_in_low
         initialize to Keep_Control
         drive SER_Q15
         set   SER_Q15     to "0"
end vector

vector   Write
         initialize to Keep_Control
         set   R_Wbar      to "0"
end vector
!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector   Y0_0
         initialize to Keep_Control
         set   Y0          to "0"
end vector

vector   Y0_1
         initialize to Keep_Control
         set   Y0          to "1"
end vector

vector   Y1_0
         initialize to Keep_Control
         set   Y1          to "0"
end vector

vector   Y1_1
         initialize to Keep_Control
         set   Y1          to "1"
end vector

vector   Y2_0
         initialize to Keep_Control
         set   Y2          to "0"
end vector

vector   Y2_1
         initialize to Keep_Control
         set   Y2          to "1"
end vector

vector   Y3_0
         initialize to Keep_Control
         set   Y3          to "0"
end vector

vector   Y3_1
         initialize to Keep_Control
         set   Y3          to "1"
end vector

vector   Y4_0
         initialize to Keep_Control
         set   Y4          to "0"
end vector

vector   Y4_1
         initialize to Keep_Control
         set   Y4          to "1"
end vector

vector   Y5_0
         initialize to Keep_Control
         set   Y5          to "0"
end vector

vector   Y5_1
         initialize to Keep_Control
         set   Y5          to "1"
end vector

vector   Y6_0
         initialize to Keep_Control
         set   Y6          to "0"
end vector

vector   Y6_1
         initialize to Keep_Control
         set   Y6          to "1"
end vector

vector   Y7_0
         initialize to Keep_Control
         set   Y7          to "0"
end vector

vector   Y7_1
         initialize to Keep_Control
         set   Y7          to "1"
end vector

vector   Y8_0
         initialize to Keep_Control
         set   Y8          to "0"
end vector

vector   Y8_1
         initialize to Keep_Control
         set   Y8          to "1"
end vector

vector   Y9_0
         initialize to Keep_Control
         set   Y9          to "0"
end vector

vector   Y9_1
         initialize to Keep_Control
         set   Y9          to "1"
end vector

vector   Y10_0
         initialize to Keep_Control
         set   Y10          to "0"
end vector

vector   Y10_1
         initialize to Keep_Control
         set   Y10          to "1"
end vector

vector   Y11_0
         initialize to Keep_Control
         set   Y11          to "0"
end vector

vector   Y11_1
         initialize to Keep_Control
         set   Y11          to "1"
end vector

vector   Y12_0
         initialize to Keep_Control
         set   Y12          to "0"
end vector

vector   Y12_1
         initialize to Keep_Control
         set   Y12          to "1"
end vector

vector   Y13_0
         initialize to Keep_Control
         set   Y13          to "0"
end vector

vector   Y13_1
         initialize to Keep_Control
         set   Y13          to "1"
end vector

vector   Y14_0
         initialize to Keep_Control
         set   Y14          to "0"
end vector

vector   Y14_1
         initialize to Keep_Control
         set   Y14          to "1"
end vector

vector   Y15_0
         initialize to Keep_Control
         set   Y15          to "0"
end vector

vector   Y15_1
         initialize to Keep_Control
         set   Y15          to "1"
end vector

!***************************************************************
!***************************************************************

!****************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with Y0.

unit "awaretest Y0 Test"
   execute Reset
   execute Write

   execute Serial_in_low
   repeat 16 times
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
   end repeat
   execute Clock_Latch
   execute Clock_Latch
   execute Y0_0

   execute Serial_in_high
   repeat 16 times
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
   end repeat
   execute Clock_Latch
   execute Clock_Latch
   execute Y0_1
end unit

unit "awaretest Y1 Test"
   execute Reset
   execute Write

   execute Serial_in_low
   repeat 16 times
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
   end repeat
   execute Clock_Latch
   execute Clock_Latch
   execute Y1_0

   execute Serial_in_high
   repeat 16 times
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
   end repeat
   execute Clock_Latch
   execute Clock_Latch
   execute Y1_1
end unit

unit "awaretest Y2 Test"
   execute Reset
   execute Write

   execute Serial_in_low
   repeat 16 times
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
   end repeat
   execute Clock_Latch
   execute Clock_Latch
   execute Y2_0

   execute Serial_in_high
   repeat 16 times
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
   end repeat
   execute Clock_Latch
   execute Clock_Latch
   execute Y2_1
end unit

unit "awaretest Y3 Test"
   execute Reset
   execute Write

   execute Serial_in_low
   repeat 16 times
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
   end repeat
   execute Clock_Latch
   execute Clock_Latch
   execute Y3_0

   execute Serial_in_high
   repeat 16 times
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
   end repeat
   execute Clock_Latch
   execute Clock_Latch
   execute Y3_1
end unit

unit "awaretest Y4 Test"
   execute Reset
   execute Write

   execute Serial_in_low
   repeat 16 times
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
   end repeat
   execute Clock_Latch
   execute Clock_Latch
   execute Y4_0

   execute Serial_in_high
   repeat 16 times
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
   end repeat
   execute Clock_Latch
   execute Clock_Latch
   execute Y4_1
end unit

unit "awaretest Y5 Test"
   execute Reset
   execute Write

   execute Serial_in_low
   repeat 16 times
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
   end repeat
   execute Clock_Latch
   execute Clock_Latch
   execute Y5_0

   execute Serial_in_high
   repeat 16 times
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
   end repeat
   execute Clock_Latch
   execute Clock_Latch
   execute Y5_1
end unit

unit "awaretest Y6 Test"
   execute Reset
   execute Write

   execute Serial_in_low
   repeat 16 times
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
   end repeat
   execute Clock_Latch
   execute Clock_Latch
   execute Y6_0

   execute Serial_in_high
   repeat 16 times
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
   end repeat
   execute Clock_Latch
   execute Clock_Latch
   execute Y6_1
end unit

unit "awaretest Y7 Test"
   execute Reset
   execute Write

   execute Serial_in_low
   repeat 16 times
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
   end repeat
   execute Clock_Latch
   execute Clock_Latch
   execute Y7_0

   execute Serial_in_high
   repeat 16 times
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
   end repeat
   execute Clock_Latch
   execute Clock_Latch
   execute Y7_1
end unit

unit "awaretest Y8 Test"
   execute Reset
   execute Write

   execute Serial_in_low
   repeat 16 times
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
   end repeat
   execute Clock_Latch
   execute Clock_Latch
   execute Y8_0

   execute Serial_in_high
   repeat 16 times
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
   end repeat
   execute Clock_Latch
   execute Clock_Latch
   execute Y8_1
end unit

unit "awaretest Y9 Test"
   execute Reset
   execute Write

   execute Serial_in_low
   repeat 16 times
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
   end repeat
   execute Clock_Latch
   execute Clock_Latch
   execute Y9_0

   execute Serial_in_high
   repeat 16 times
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
   end repeat
   execute Clock_Latch
   execute Clock_Latch
   execute Y9_1
end unit

unit "awaretest Y10 Test"
   execute Reset
   execute Write

   execute Serial_in_low
   repeat 16 times
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
   end repeat
   execute Clock_Latch
   execute Clock_Latch
   execute Y10_0

   execute Serial_in_high
   repeat 16 times
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
   end repeat
   execute Clock_Latch
   execute Clock_Latch
   execute Y10_1
end unit

unit "awaretest Y11 Test"
   execute Reset
   execute Write

   execute Serial_in_low
   repeat 16 times
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
   end repeat
   execute Clock_Latch
   execute Clock_Latch
   execute Y11_0

   execute Serial_in_high
   repeat 16 times
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
   end repeat
   execute Clock_Latch
   execute Clock_Latch
   execute Y11_1
end unit

unit "awaretest Y12 Test"
   execute Reset
   execute Write

   execute Serial_in_low
   repeat 16 times
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
   end repeat
   execute Clock_Latch
   execute Clock_Latch
   execute Y12_0

   execute Serial_in_high
   repeat 16 times
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
   end repeat
   execute Clock_Latch
   execute Clock_Latch
   execute Y12_1
end unit

unit "awaretest Y13 Test"
   execute Reset
   execute Write

   execute Serial_in_low
   repeat 16 times
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
   end repeat
   execute Clock_Latch
   execute Clock_Latch
   execute Y13_0

   execute Serial_in_high
   repeat 16 times
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
   end repeat
   execute Clock_Latch
   execute Clock_Latch
   execute Y13_1
end unit

unit "awaretest Y14 Test"
   execute Reset
   execute Write

   execute Serial_in_low
   repeat 16 times
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
   end repeat
   execute Clock_Latch
   execute Clock_Latch
   execute Y14_0

   execute Serial_in_high
   repeat 16 times
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
   end repeat
   execute Clock_Latch
   execute Clock_Latch
   execute Y14_1
end unit

unit "awaretest Y15 Test"
   execute Reset
   execute Write

   execute Serial_in_low
   repeat 16 times
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
   end repeat
   execute Clock_Latch
   execute Clock_Latch
   execute Y15_0

   execute Serial_in_high
   repeat 16 times
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
   end repeat
   execute Clock_Latch
   execute Clock_Latch
   execute Y15_1
end unit


unit  "unit1 test shift register and latch"
   execute Reset
   execute Write

   repeat 8 times
   execute Serial_in_low
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
   execute Serial_in_high
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
   end repeat
      execute Clock_Latch
      execute Clock_Latch
   execute Data_out_55

   execute Serial_in_low
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Latch
      execute Clock_Latch
   execute Data_out_AA
end   unit

unit  "unit2 test parallel load of shift register"
   execute Reset
   execute Write

   repeat 8 times
   execute Serial_in_low
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
   execute Serial_in_high
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
   end repeat
      execute Clock_Latch
      execute Clock_Latch
   execute Data_out_55

   execute Serial_in_low
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
   execute Read
   execute Mode_high
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute Mode_low
      execute Clock_Latch
      execute Clock_Latch
   execute Data_out_55
   execute Q15_low
      execute Clock_Shift_Register
      execute Clock_Shift_Register
   execute Q15_high
end   unit

unit  "unit3 test Clear"
   execute Reset
   execute Write
   execute Serial_in_high
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Latch
      execute Clock_Latch
   execute Clear_Latch
   execute Data_out_00
end   unit

unit  "unit4 test Chip not selected"
   execute Reset
   execute Write
   execute CSbar_high
   execute Serial_in_high
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Shift_Register_Serial_Data
      execute Clock_Latch
      execute Clock_Latch
   execute Data_out_00
end   unit

!End of test