!!!!    6    0    1  989258772  Vd17e                                         

! Device           : 82s123
! Function         : PROM, 32 x 8  tri-state outputs
! revision         : B.01.00
! safeguard        : standard_sttl
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

sequential

! warning "Pull-ups are required to test high-impedance outputs."

vector cycle 500n
receive delay 400n

assign VCC to pins 16
assign GND to pins 8

assign Address_Bus  to pins 14,13,12,11,10
assign Data_Bus     to pins 9,7,6,5,4,3,2,1
assign Data_D0      to pins 1    !AT Added for minimum pin test.
assign Data_D1      to pins 2    !AT Added for minimum pin test.
assign Data_D2      to pins 3    !AT Added for minimum pin test.
assign Data_D3      to pins 4    !AT Added for minimum pin test.
assign Data_D4      to pins 5    !AT Added for minimum pin test.
assign Data_D5      to pins 6    !AT Added for minimum pin test.
assign Data_D6      to pins 7    !AT Added for minimum pin test.
assign Data_D7      to pins 9    !AT Added for minimum pin test.

assign Chip_Enable  to pins 15
assign Disable_pins to pins 15

family TTL

power VCC,GND

inputs Address_Bus, Chip_Enable

outputs Data_Bus
outputs Data_D0, Data_D1, Data_D2, Data_D3 !AT Added for minimum pin test.
outputs Data_D4, Data_D5, Data_D6, Data_D7 !AT Added for minimum pin test.

disable Data_Bus with Disable_pins to "1"

when Disable_pins is "1" inactive Data_Bus
trace Data_Bus to Address_Bus, Chip_Enable

set load on groups  Data_Bus  to pull up

!**********************************************************
!**********************************************************

vector    Address_Counter
 set Chip_Enable       to   "0"
 set Address_Bus       to   "00000"
 set Data_Bus          to   "00000000"
 upcounter Address_Bus
end vector

vector    Address_00000_CS_false_0
 set Chip_Enable       to   "1"
 set Address_Bus       to   "11111"
 set Data_Bus          to   "00000000"
end vector

vector    Address_00000_CS_false_1
 set Chip_Enable       to   "1"
 set Address_Bus       to   "11111"
 set Data_Bus          to   "11111111"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector    Address_Counter_D0
 set Chip_Enable       to   "0"
 set Address_Bus       to   "00000"
 set Data_D0           to   "0"
 upcounter Address_Bus
end vector

vector    Address_Counter_D1
 set Chip_Enable       to   "0"
 set Address_Bus       to   "00000"
 set Data_D1           to   "0"
 upcounter Address_Bus
end vector

vector    Address_Counter_D2
 set Chip_Enable       to   "0"
 set Address_Bus       to   "00000"
 set Data_D2           to   "0"
 upcounter Address_Bus
end vector

vector    Address_Counter_D3
 set Chip_Enable       to   "0"
 set Address_Bus       to   "00000"
 set Data_D3           to   "0"
 upcounter Address_Bus
end vector

vector    Address_Counter_D4
 set Chip_Enable       to   "0"
 set Address_Bus       to   "00000"
 set Data_D4           to   "0"
 upcounter Address_Bus
end vector

vector    Address_Counter_D5
 set Chip_Enable       to   "0"
 set Address_Bus       to   "00000"
 set Data_D5           to   "0"
 upcounter Address_Bus
end vector

vector    Address_Counter_D6
 set Chip_Enable       to   "0"
 set Address_Bus       to   "00000"
 set Data_D6           to   "0"
 upcounter Address_Bus
end vector

vector    Address_Counter_D7
 set Chip_Enable       to   "0"
 set Address_Bus       to   "00000"
 set Data_D7           to   "0"
 upcounter Address_Bus
end vector

!**********************************************************
!**********************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit "awaretest D0 Test"
 preset counter Address_Counter_D0   compress
  repeat 31 times
  count Address_Counter_D0   compress
 end repeat
end unit

unit "awaretest D1 Test"
 preset counter Address_Counter_D1   compress
  repeat 31 times
  count Address_Counter_D1   compress
 end repeat
end unit

unit "awaretest D2 Test"
 preset counter Address_Counter_D2   compress
  repeat 31 times
  count Address_Counter_D2   compress
 end repeat
end unit

unit "awaretest D3 Test"
 preset counter Address_Counter_D3   compress
  repeat 31 times
  count Address_Counter_D3   compress
 end repeat
end unit

unit "awaretest D4 Test"
 preset counter Address_Counter_D4   compress
  repeat 31 times
  count Address_Counter_D4   compress
 end repeat
end unit

unit "awaretest D5 Test"
 preset counter Address_Counter_D5   compress
  repeat 31 times
  count Address_Counter_D5   compress
 end repeat
end unit

unit "awaretest D6 Test"
 preset counter Address_Counter_D6   compress
  repeat 31 times
  count Address_Counter_D6   compress
 end repeat
end unit

unit "awaretest D7 Test"
 preset counter Address_Counter_D7   compress
  repeat 31 times
  count Address_Counter_D7   compress
 end repeat
end unit

unit "Complete ROM Test"
 preset counter Address_Counter   compress
  repeat 31 times
  count Address_Counter   compress
 end repeat
end unit

!  Test for CS (pin 15) SA0 with pull-up resistor to VCC.
unit "Test Chip_Enable false"
 execute   Address_00000_CS_false_1
end unit

! end of test