!!!! 6 0 1 989967049 V7d50 gh_out_ttl ! Device : 82s321 ! Function : prom 3-state 4096 x 8 ! revision : B.01.00 ! safeguard : standard_ttl ! Modifications : Modified for AwareTest xi ! warning "This library has not been verified with hardware." sequential assign VCC to pins 24 assign GND to pins 12 assign Data_output to pins 17,16,15,14,13,11,10,9 assign Data_D0 to pins 9 !AT Added for minimum pin test. assign Data_D1 to pins 10 !AT Added for minimum pin test. assign Data_D2 to pins 11 !AT Added for minimum pin test. assign Data_D3 to pins 13 !AT Added for minimum pin test. assign Data_D4 to pins 14 !AT Added for minimum pin test. assign Data_D5 to pins 15 !AT Added for minimum pin test. assign Data_D6 to pins 16 !AT Added for minimum pin test. assign Data_D7 to pins 17 !AT Added for minimum pin test. assign Address to pins 19,21,22,23,1,2,3,4,5,6,7,8 assign Chip_Enable_1_bar to pins 20 assign Chip_Enable_2 to pins 18 family TTL power VCC, GND inputs Address, Chip_Enable_1_bar, Chip_Enable_2 outputs Data_output outputs Data_D0, Data_D1, Data_D2, Data_D3 !AT Added for minimum pin test. outputs Data_D4, Data_D5, Data_D6, Data_D7 !AT Added for minimum pin test. disable Data_output with Chip_Enable_1_bar to "1" disable Data_output with Chip_Enable_2 to "0" when Chip_Enable_1_bar is "1" inactive Data_output when Chip_Enable_2 is "0" inactive Data_output ! Note: default trace specification is used !********************************************************************* !********************************************************************* vector Count_vector_1 set Chip_Enable_1_bar to "0" set Chip_Enable_2 to "1" set Data_output to "00000000" set Address to "0000 0000 0000" upcounter Address end vector vector Count_vector_2 set Chip_Enable_1_bar to "0" set Chip_Enable_2 to "1" set Data_output to "00000000" set Address to "1111 1111 1111" downcounter Address end vector !AT The following vectors have been added for a minimum pins test. Any !AT vectors that references the data bus was copied and modified to reference !AT only a single pin of the data bus. vector Count_vector_D0 set Chip_Enable_1_bar to "0" set Chip_Enable_2 to "1" set Data_D0 to "0" set Address to "0000 0000 0000" upcounter Address end vector vector Count_vector_D1 set Chip_Enable_1_bar to "0" set Chip_Enable_2 to "1" set Data_D1 to "0" set Address to "0000 0000 0000" upcounter Address end vector vector Count_vector_D2 set Chip_Enable_1_bar to "0" set Chip_Enable_2 to "1" set Data_D2 to "0" set Address to "0000 0000 0000" upcounter Address end vector vector Count_vector_D3 set Chip_Enable_1_bar to "0" set Chip_Enable_2 to "1" set Data_D3 to "0" set Address to "0000 0000 0000" upcounter Address end vector vector Count_vector_D4 set Chip_Enable_1_bar to "0" set Chip_Enable_2 to "1" set Data_D4 to "0" set Address to "0000 0000 0000" upcounter Address end vector vector Count_vector_D5 set Chip_Enable_1_bar to "0" set Chip_Enable_2 to "1" set Data_D5 to "0" set Address to "0000 0000 0000" upcounter Address end vector vector Count_vector_D6 set Chip_Enable_1_bar to "0" set Chip_Enable_2 to "1" set Data_D6 to "0" set Address to "0000 0000 0000" upcounter Address end vector vector Count_vector_D7 set Chip_Enable_1_bar to "0" set Chip_Enable_2 to "1" set Data_D7 to "0" set Address to "0000 0000 0000" upcounter Address end vector !********************************************************************* !********************************************************************* !AT The following AwareTest units have been added for minimum pins tests. Each !AT unit tests a separate data pin starting with D0. unit "awaretest D0 Test" preset counter Count_vector_D0 compress repeat 255 times count Count_vector_D0 compress end repeat end unit unit "awaretest D1 Test" preset counter Count_vector_D1 compress repeat 255 times count Count_vector_D1 compress end repeat end unit unit "awaretest D2 Test" preset counter Count_vector_D2 compress repeat 255 times count Count_vector_D2 compress end repeat end unit unit "awaretest D3 Test" preset counter Count_vector_D3 compress repeat 255 times count Count_vector_D3 compress end repeat end unit unit "awaretest D4 Test" preset counter Count_vector_D4 compress repeat 255 times count Count_vector_D4 compress end repeat end unit unit "awaretest D5 Test" preset counter Count_vector_D5 compress repeat 255 times count Count_vector_D5 compress end repeat end unit unit "awaretest D6 Test" preset counter Count_vector_D6 compress repeat 255 times count Count_vector_D6 compress end repeat end unit unit "awaretest D7 Test" preset counter Count_vector_D7 compress repeat 255 times count Count_vector_D7 compress end repeat end unit unit "ROM: test lower half" preset counter Count_vector_1 compress repeat 2048 times count Count_vector_1 compress end repeat end unit unit "ROM: test upper half" preset counter Count_vector_2 compress repeat 2048 times count Count_vector_2 compress end repeat end unit ! End of test