!!!!    6    0    1  990709459  V190f                                         

! Device           : 2907
! Function         : latched_bus_transceiver oc d_type_with_parity quad
! revision         : B.01.00
! safeguard        : high_out_lsttl
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

sequential

vector cycle 2000n
receive delay 1900n

assign  VCC         to pins   20
assign  GND         to pins   5,15

assign  A_inputs    to pins   3,7,13,17
assign  A0_I        to pins   3         !AT Added for minimum pin test.
assign  A1_I        to pins   7         !AT Added for minimum pin test.
assign  A2_I        to pins   13        !AT Added for minimum pin test.
assign  A3_I        to pins   17        !AT Added for minimum pin test.

assign  Bus_bar           to pins   4,6,14,16
assign  Bus0        to pins   4         !AT Added for minimum pin test.
assign  Bus1        to pins   6         !AT Added for minimum pin test.
assign  Bus2        to pins   14        !AT Added for minimum pin test.
assign  Bus3        to pins   16        !AT Added for minimum pin test.

assign  Receiver_outputs to pins   2,8,12,18
assign  R0_O        to pins   2         !AT Added for minimum pin test.
assign  R1_O        to pins   8         !AT Added for minimum pin test.
assign  R2_O        to pins   12        !AT Added for minimum pin test.
assign  R3_O        to pins   18        !AT Added for minimum pin test.

assign  Driver_clock       to pins   19
assign  Parity_output      to pins   10
assign  Bus_enable_bar     to pins   9
assign  RLE_bar            to pins   1
assign  Output_enable_bar  to pins   11

family    TTL

power   VCC, GND

inputs  A_inputs, Driver_clock
inputs  Bus_enable_bar, RLE_bar, Output_enable_bar
inputs  A0_I, A1_I, A2_I, A3_I         !AT Added for minimum pin test.

outputs Receiver_outputs, Parity_output
outputs R0_O, R1_O, R2_O, R3_O         !AT Added for minimum pin test.

bidirectional Bus_bar
bidirectional Bus0, Bus1, Bus2, Bus3   !AT Added for minimum pin test.

when  Bus_enable_bar    is    "1"   inputs   Bus_bar
when  Bus_enable_bar    is    "0"   outputs  Bus_bar

when  Output_enable_bar is    "1"   inactive Receiver_outputs

trace   Receiver_outputs  to  A_inputs, Driver_clock,Bus_bar
trace   Receiver_outputs  to  Bus_enable_bar,RLE_bar,Output_enable_bar

trace   Parity_output     to  A_inputs, Driver_clock,Bus_bar
trace   Parity_output     to  Bus_enable_bar, RLE_bar, Output_enable_bar

trace   Bus_bar           to  A_inputs, Driver_clock
trace   Bus_bar           to  Bus_enable_bar

disable Bus_bar            with Bus_enable_bar     to    "1"
disable Receiver_outputs   with Output_enable_bar  to    "1"

!*********************************************************************
!*********************************************************************

vector    Bus_enable
     set  Bus_enable_bar to   "0"
     set  Driver_clock   to   "0"
end vector

vector    RLE_bar_low
     set  Bus_enable_bar to   "1"
     set  RLE_bar        to   "0"
end vector

vector    Bus_in_1111
     drive     Bus_bar
     set  RLE_bar        to   "k"
     set  Bus_enable_bar to   "1"
     set  Bus_bar        to   "1111"
end vector


vector    RLE_bar_high
     initialize to       Bus_in_1111
     set  RLE_bar        to   "1"
end vector

vector    Clock_high
     set  A_inputs       to   "kkkk"
     set  Driver_clock   to   "1"
end vector

vector    Clock_low
     set  Driver_clock   to   "0"
end vector

vector    A_inputs_0000
     initialize to       Bus_enable
     set  A_inputs       to   "0000"
end vector

vector    A_inputs_0001
     initialize to       Bus_enable
     set  A_inputs       to   "0001"
end vector

vector    A_inputs_0011
     initialize to       Bus_enable
     set  A_inputs       to   "0011"
end vector

vector    A_inputs_0111
     initialize to       Bus_enable
     set  A_inputs       to   "0111"
end vector

vector    A_inputs_1111
     initialize to       Bus_enable
     set  A_inputs       to   "1111"
end vector

vector    Bus_in_0000
     drive     Bus_bar
     set  RLE_bar        to   "k"
     set  Bus_enable_bar to   "1"
     set  Bus_bar        to   "0000"
end vector

vector    Bus_in_0001
     drive     Bus_bar
     set  RLE_bar        to   "k"
     set  Bus_enable_bar to   "1"
     set  Bus_bar        to   "0001"
end vector

vector    Bus_in_0011
     drive     Bus_bar
     set  RLE_bar        to   "k"
     set  Bus_enable_bar to   "1"
     set  Bus_bar        to   "0011"
end vector

vector    Bus_in_0111
     drive     Bus_bar
     set  RLE_bar        to   "k"
     set  Bus_enable_bar to   "1"
     set  Bus_bar        to   "0111"
end vector

vector    Bus_out_0000
     receive   Bus_bar
     set  Driver_clock   to   "0"
     set  Bus_enable_bar to   "0"
     set  Bus_bar        to   "0000"
end vector

vector    Bus_out_1000
     receive   Bus_bar
     set  Driver_clock   to   "0"
     set  Bus_enable_bar to   "0"
     set  Bus_bar        to   "1000"
end vector

vector    Bus_out_1100
     receive   Bus_bar
     set  Driver_clock   to   "0"
     set  Bus_enable_bar to   "0"
     set  Bus_bar        to   "1100"
end vector

vector    Bus_out_1110
     receive   Bus_bar
     set  Driver_clock   to   "0"
     set  Bus_enable_bar to   "0"
     set  Bus_bar        to   "1110"
end vector

vector    Bus_out_1111
     receive   Bus_bar
     set  Driver_clock   to   "0"
     set  Bus_enable_bar to   "0"
     set  Bus_bar        to   "1111"
end vector

vector    Parity_Generate_0
     initialize          to   Bus_enable
     set  A_inputs       to   "kkkk"
     set  Parity_output  to   "0"
end vector

vector    Parity_Generate_1
     initialize          to   Bus_enable
     set  A_inputs       to   "kkkk"
     set  Parity_output  to   "1"
end vector

vector    Parity_Check_0
     drive    Bus_bar
     set  Bus_bar           to   "kkkk"
     set  RLE_bar           to   "k"
     set  Bus_enable_bar    to   "1"
     set  Output_enable_bar to   "0"
     set  Parity_output     to   "0"
end vector

vector    Parity_Check_1
     drive    Bus_bar
     set  Bus_bar           to   "kkkk"
     set  RLE_bar           to   "k"
     set  Bus_enable_bar    to   "1"
     set  Output_enable_bar to   "0"
     set  Parity_output     to   "1"
end vector

vector    Receiver_outputs_1111
     drive     Bus_bar
     set  Bus_bar            to   "kkkk"
     set  RLE_bar            to   "k"
     set  Bus_enable_bar     to   "1"
     set  Output_enable_bar  to   "0"
     set  Receiver_outputs   to   "1111"
end vector

vector    Receiver_outputs_1110
     drive     Bus_bar
     set  Bus_bar            to   "kkkk"
     set  RLE_bar            to   "k"
     set  Bus_enable_bar     to   "1"
     set  Output_enable_bar  to   "0"
     set  Receiver_outputs   to   "1110"
end vector

vector    Receiver_outputs_1100
     drive     Bus_bar
     set  Bus_bar            to   "kkkk"
     set  RLE_bar            to   "k"
     set  Bus_enable_bar     to   "1"
     set  Output_enable_bar  to   "0"
     set  Receiver_outputs   to   "1100"
end vector

vector    Receiver_outputs_1000
     drive     Bus_bar
     set  Bus_bar            to   "kkkk"
     set  RLE_bar            to   "k"
     set  Bus_enable_bar     to   "1"
     set  Output_enable_bar  to   "0"
     set  Receiver_outputs   to   "1000"
end vector

vector    Receiver_outputs_0000
     drive     Bus_bar
     set  Bus_bar            to   "kkkk"
     set  RLE_bar            to   "k"
     set  Bus_enable_bar     to   "1"
     set  Output_enable_bar  to   "0"
     set  Receiver_outputs   to   "0000"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector    Clock_high_A0
     set  A0_I           to   "k"
     set  Driver_clock   to   "1"
end vector

vector    Clock_high_A1
     set  A1_I           to   "k"
     set  Driver_clock   to   "1"
end vector

vector    Clock_high_A2
     set  A2_I           to   "k"
     set  Driver_clock   to   "1"
end vector

vector    Clock_high_A3
     set  A3_I           to   "k"
     set  Driver_clock   to   "1"
end vector

vector    A0_I_0
     initialize to       Bus_enable
     set  A0_I           to   "0"
end vector

vector    A0_I_1
     initialize to       Bus_enable
     set  A0_I           to   "1"
end vector

vector    A1_I_0
     initialize to       Bus_enable
     set  A1_I           to   "0"
end vector

vector    A1_I_1
     initialize to       Bus_enable
     set  A1_I           to   "1"
end vector

vector    A2_I_0
     initialize to       Bus_enable
     set  A2_I           to   "0"
end vector

vector    A2_I_1
     initialize to       Bus_enable
     set  A2_I           to   "1"
end vector

vector    A3_I_0
     initialize to       Bus_enable
     set  A3_I           to   "0"
end vector

vector    A3_I_1
     initialize to       Bus_enable
     set  A3_I           to   "1"
end vector

vector    Bus0_out_0
     receive   Bus0
     set  Driver_clock   to   "0"
     set  Bus_enable_bar to   "0"
     set  Bus0           to   "0"
end vector

vector    Bus0_out_1
     receive   Bus0
     set  Driver_clock   to   "0"
     set  Bus_enable_bar to   "0"
     set  Bus0           to   "1"
end vector

vector    Bus1_out_0
     receive   Bus1
     set  Driver_clock   to   "0"
     set  Bus_enable_bar to   "0"
     set  Bus1           to   "0"
end vector

vector    Bus1_out_1
     receive   Bus1
     set  Driver_clock   to   "0"
     set  Bus_enable_bar to   "0"
     set  Bus1           to   "1"
end vector

vector    Bus2_out_0
     receive   Bus2
     set  Driver_clock   to   "0"
     set  Bus_enable_bar to   "0"
     set  Bus2           to   "0"
end vector

vector    Bus2_out_1
     receive   Bus2
     set  Driver_clock   to   "0"
     set  Bus_enable_bar to   "0"
     set  Bus2           to   "1"
end vector

vector    Bus3_out_0
     receive   Bus3
     set  Driver_clock   to   "0"
     set  Bus_enable_bar to   "0"
     set  Bus3           to   "0"
end vector

vector    Bus3_out_1
     receive   Bus3
     set  Driver_clock   to   "0"
     set  Bus_enable_bar to   "0"
     set  Bus3           to   "1"
end vector

vector    Bus0_in_0
     drive     Bus0
     set  RLE_bar        to   "k"
     set  Bus_enable_bar to   "1"
     set  Bus0           to   "0"
end vector

vector    Bus0_in_1
     drive     Bus0
     set  RLE_bar        to   "k"
     set  Bus_enable_bar to   "1"
     set  Bus0           to   "1"
end vector

vector    Bus1_in_0
     drive     Bus1
     set  RLE_bar        to   "k"
     set  Bus_enable_bar to   "1"
     set  Bus1           to   "0"
end vector

vector    Bus1_in_1
     drive     Bus1
     set  RLE_bar        to   "k"
     set  Bus_enable_bar to   "1"
     set  Bus1           to   "1"
end vector

vector    Bus2_in_0
     drive     Bus2
     set  RLE_bar        to   "k"
     set  Bus_enable_bar to   "1"
     set  Bus2           to   "0"
end vector

vector    Bus2_in_1
     drive     Bus2
     set  RLE_bar        to   "k"
     set  Bus_enable_bar to   "1"
     set  Bus2           to   "1"
end vector

vector    Bus3_in_0
     drive     Bus3
     set  RLE_bar        to   "k"
     set  Bus_enable_bar to   "1"
     set  Bus3           to   "0"
end vector

vector    Bus3_in_1
     drive     Bus3
     set  RLE_bar        to   "k"
     set  Bus_enable_bar to   "1"
     set  Bus3           to   "1"
end vector

vector    R0_outputs_0
     drive     Bus0
     set  Bus0               to   "k"
     set  RLE_bar            to   "k"
     set  Bus_enable_bar     to   "1"
     set  Output_enable_bar  to   "0"
     set  R0_O               to   "0"
end vector

vector    R0_outputs_1
     drive     Bus0
     set  Bus0               to   "k"
     set  RLE_bar            to   "k"
     set  Bus_enable_bar     to   "1"
     set  Output_enable_bar  to   "0"
     set  R0_O               to   "1"
end vector

vector    R1_outputs_0
     drive     Bus1
     set  Bus1               to   "k"
     set  RLE_bar            to   "k"
     set  Bus_enable_bar     to   "1"
     set  Output_enable_bar  to   "0"
     set  R1_O               to   "0"
end vector

vector    R1_outputs_1
     drive     Bus1
     set  Bus1               to   "k"
     set  RLE_bar            to   "k"
     set  Bus_enable_bar     to   "1"
     set  Output_enable_bar  to   "0"
     set  R1_O               to   "1"
end vector

vector    R2_outputs_0
     drive     Bus2
     set  Bus2               to   "k"
     set  RLE_bar            to   "k"
     set  Bus_enable_bar     to   "1"
     set  Output_enable_bar  to   "0"
     set  R2_O               to   "0"
end vector

vector    R2_outputs_1
     drive     Bus2
     set  Bus2               to   "k"
     set  RLE_bar            to   "k"
     set  Bus_enable_bar     to   "1"
     set  Output_enable_bar  to   "0"
     set  R2_O               to   "1"
end vector

vector    R3_outputs_0
     drive     Bus3
     set  Bus3               to   "k"
     set  RLE_bar            to   "k"
     set  Bus_enable_bar     to   "1"
     set  Output_enable_bar  to   "0"
     set  R3_O               to   "0"
end vector

vector    R3_outputs_1
     drive     Bus3
     set  Bus3               to   "k"
     set  RLE_bar            to   "k"
     set  Bus_enable_bar     to   "1"
     set  Output_enable_bar  to   "0"
     set  R3_O               to   "1"
end vector

!*********************************************************************
!*********************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with A0.

unit "awaretest A0 input Test"
     execute   A0_I_0
     execute   Clock_high_A0
     execute   Clock_low
     execute   Bus0_out_1
     execute   A0_I_1
     execute   Clock_high_A0
     execute   Clock_low
     execute   Bus0_out_0
end unit

unit "awaretest A1 input Test"
     execute   A1_I_0
     execute   Clock_high_A1
     execute   Clock_low
     execute   Bus1_out_1
     execute   A1_I_1
     execute   Clock_high_A1
     execute   Clock_low
     execute   Bus1_out_0
end unit

unit "awaretest A2 input Test"
     execute   A2_I_0
     execute   Clock_high_A2
     execute   Clock_low
     execute   Bus2_out_1
     execute   A2_I_1
     execute   Clock_high_A2
     execute   Clock_low
     execute   Bus2_out_0
end unit

unit "awaretest A3 input Test"
     execute   A3_I_0
     execute   Clock_high_A3
     execute   Clock_low
     execute   Bus3_out_1
     execute   A3_I_1
     execute   Clock_high_A3
     execute   Clock_low
     execute   Bus3_out_0
end unit

unit "awaretest R1 input Test"
     execute   RLE_bar_low
     execute   Bus0_in_0
     execute   R0_outputs_1
     execute   Bus0_in_1
     execute   R0_outputs_0
end unit

unit "awaretest R1 input Test"
     execute   RLE_bar_low
     execute   Bus1_in_0
     execute   R1_outputs_1
     execute   Bus1_in_1
     execute   R1_outputs_0
end unit

unit "awaretest R2 input Test"
     execute   RLE_bar_low
     execute   Bus2_in_0
     execute   R2_outputs_1
     execute   Bus2_in_1
     execute   R2_outputs_0
end unit

unit "awaretest R3 input Test"
     execute   RLE_bar_low
     execute   Bus3_in_0
     execute   R3_outputs_1
     execute   Bus3_in_1
     execute   R3_outputs_0
end unit


unit "Test A_inputs"
     execute   A_inputs_0000
     execute   Parity_Generate_0
     execute   Clock_high
     execute   Clock_low
     execute   Bus_out_1111
     execute   A_inputs_0001
     execute   Parity_Generate_1
     execute   Clock_high
     execute   Clock_low
     execute   Bus_out_1110
     execute   A_inputs_0011
     execute   Parity_Generate_0
     execute   Clock_high
     execute   Clock_low
     execute   Bus_out_1100
     execute   A_inputs_0111
     execute   Parity_Generate_1
     execute   Clock_high
     execute   Clock_low
     execute   Bus_out_1000
     execute   A_inputs_1111
     execute   Parity_Generate_0
     execute   Clock_high
     execute   Clock_low
     execute   Bus_out_0000
end unit

unit "Test receivers, RLE_bar available"
     execute   RLE_bar_low
     execute   Bus_in_0000
     execute   Parity_Check_0
     execute   Receiver_outputs_1111
     execute   Bus_in_0001
     execute   Parity_Check_1
     execute   Receiver_outputs_1110
     execute   Bus_in_0011
     execute   Parity_Check_0
     execute   Receiver_outputs_1100
     execute   Bus_in_0111
     execute   Parity_Check_1
     execute   Receiver_outputs_1000
     execute   Bus_in_1111
     execute   Parity_Check_0
     execute   Receiver_outputs_0000
     execute   RLE_bar_high
     execute   Bus_in_0000
     execute   Receiver_outputs_0000
end unit

unit "Test receivers, RLE_bar tied low"
     execute   RLE_bar_low
     execute   Bus_in_0000
     execute   Parity_Check_0
     execute   Receiver_outputs_1111
     execute   Bus_in_0001
     execute   Parity_Check_1
     execute   Receiver_outputs_1110
     execute   Bus_in_0011
     execute   Parity_Check_0
     execute   Receiver_outputs_1100
     execute   Bus_in_0111
     execute   Parity_Check_1
     execute   Receiver_outputs_1000
     execute   Bus_in_1111
     execute   Parity_Check_0
     execute   Receiver_outputs_0000
end unit

!    End of test