!!!!    6    0    1  991664127  Vc099                                         

!  $Log: <@(#) A.10.00  New library.> $

!-----------------------------------------------------------------------
!  Copyright (c) Hewlett-Packard Co. 1996
!
!  All Rights Reserved.  Reproduction, adaptation, or translation
!  without prior written permission is prohibited, except as allowed
!  under the copyright laws.
!
!-----------------------------------------------------------------------
!
! Device           : 74f656
! Function         : Octal buffer with Parity (3-state)
! revision         : B.01.00
! safeguard        : high_out_fttl
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

! Manufacturer  : PHILIPS
! Package       : 24 pin Dip
! Test Platform : HP3070
!
!-----------------------------------------------------------------------
!
! Additional Information.
!
!       1.     Chip Marking:
!                       74F656AN
!                       KQL0408
!                       9448hf
!
!       2.     Ordering Information:
!                       Part Number             Package
!                       N74F656AN               24pin Slim DIP (300mil)
!                       N74F656AD               24pin Slim SOL (300mil)
!------------------------------------------------------------------------------

combinatorial

vector cycle 1000n
receive delay 800n

assign   VCC            to pins  24
assign   GND            to pins  12

assign   ParityIn_I     to pins   3
assign   OEbar_I        to pins  23,  2,  1
assign   DataIn_I       to pins  11, 10,  9,  8,  7,  6,  5,  4
assign   D0_I           to pins   4            !AT Added for minimum pin test.
assign   D1_I           to pins   5            !AT Added for minimum pin test.
assign   D2_I           to pins   6            !AT Added for minimum pin test.
assign   D3_I           to pins   7            !AT Added for minimum pin test.
assign   D4_I           to pins   8            !AT Added for minimum pin test.
assign   D5_I           to pins   9            !AT Added for minimum pin test.
assign   D6_I           to pins  10            !AT Added for minimum pin test.
assign   D7_I           to pins  11            !AT Added for minimum pin test.

assign   ODDParity_O    to pins  22
assign   EvenParity_O   to pins  21
assign   DataOutBar_O   to pins  13, 14, 15, 16, 17, 18, 19, 20
assign   D0_O           to pins  20            !AT Added for minimum pin test.
assign   D1_O           to pins  19            !AT Added for minimum pin test.
assign   D2_O           to pins  18            !AT Added for minimum pin test.
assign   D3_O           to pins  17            !AT Added for minimum pin test.
assign   D4_O           to pins  16            !AT Added for minimum pin test.
assign   D5_O           to pins  15            !AT Added for minimum pin test.
assign   D6_O           to pins  14            !AT Added for minimum pin test.
assign   D7_O           to pins  13            !AT Added for minimum pin test.

assign   Disable_pins   to pins   1,  2, 23

family   TTL

format hexadecimal   DataOutBar_O, DataIn_I

power    VCC, GND

inputs   ParityIn_I, OEbar_I, DataIn_I
inputs   D0_I, D1_I, D2_I, D3_I       !AT Added for minimum pin test.
inputs   D4_I, D5_I, D6_I, D7_I       !AT Added for minimum pin test.

outputs  ODDParity_O, EvenParity_O, DataOutBar_O
outputs  D0_O, D1_O, D2_O, D3_O       !AT Added for minimum pin test.
outputs  D4_O, D5_O, D6_O, D7_O       !AT Added for minimum pin test.

disable  DataOutBar_O with Disable_pins to "X1X"
disable  DataOutBar_O with Disable_pins to "1XX"
disable  DataOutBar_O with Disable_pins to "XX1"
disable  ODDParity_O  with Disable_pins to "X1X"
disable  ODDParity_O  with Disable_pins to "1XX"
disable  ODDParity_O  with Disable_pins to "XX1"
disable  EvenParity_O with Disable_pins to "X1X"
disable  EvenParity_O with Disable_pins to "1XX"
disable  EvenParity_O with Disable_pins to "XX1"

set load on  groups DataOutBar_O to pull up
set load on  groups EvenParity_O to pull up
set load on  groups ODDParity_O  to pull up

!
!-----------------------------------------------------------------------
!

vector  DataIn_55
   set   OEbar_I        to "000"
   set   DataIn_I       to "55"
   set   DataOutBar_O   to "55"
end vector

vector  DataIn_55_Disabled_OE2
   set   OEbar_I        to "100"
   set   DataIn_I       to "55"
   set   DataOutBar_O   to "FF"
   set   EvenParity_O   to "1"
   set   ODDParity_O    to "1"
end vector

vector  DataIn_55_Disabled_OE1
   set   OEbar_I        to "010"
   set   DataIn_I       to "55"
   set   DataOutBar_O   to "FF"
   set   EvenParity_O   to "1"
   set   ODDParity_O    to "1"
end vector

vector  DataIn_55_Disabled_OE0
   set   OEbar_I        to "001"
   set   DataIn_I       to "55"
   set   DataOutBar_O   to "FF"
   set   EvenParity_O   to "1"
   set   ODDParity_O    to "1"
end vector

vector  DataIn_55_Parity_odd
   set   ParityIn_I     to "0"
   set   OEbar_I        to "000"
   set   DataIn_I       to "55"
   set   EvenParity_O   to "1"
   set   ODDParity_O    to "0"
end vector

vector  DataIn_55_Parity_even
   set   ParityIn_I     to "1"
   set   OEbar_I        to "000"
   set   DataIn_I       to "55"
   set   EvenParity_O   to "0"
   set   ODDParity_O    to "1"
end vector

vector  DataIn_AA
   set   OEbar_I        to "000"
   set   DataIn_I       to "AA"
   set   DataOutBar_O   to "AA"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector  D0_I_0
   set   OEbar_I        to "000"
   set   D0_I           to "0"
   set   D0_O           to "0"
end vector

vector  D0_I_1
   set   OEbar_I        to "000"
   set   D0_I           to "1"
   set   D0_O           to "1"
end vector

vector  D1_I_0
   set   OEbar_I        to "000"
   set   D1_I           to "0"
   set   D1_O           to "0"
end vector

vector  D1_I_1
   set   OEbar_I        to "000"
   set   D1_I           to "1"
   set   D1_O           to "1"
end vector

vector  D2_I_0
   set   OEbar_I        to "000"
   set   D2_I           to "0"
   set   D2_O           to "0"
end vector

vector  D2_I_1
   set   OEbar_I        to "000"
   set   D2_I           to "1"
   set   D2_O           to "1"
end vector

vector  D3_I_0
   set   OEbar_I        to "000"
   set   D3_I           to "0"
   set   D3_O           to "0"
end vector

vector  D3_I_1
   set   OEbar_I        to "000"
   set   D3_I           to "1"
   set   D3_O           to "1"
end vector

vector  D4_I_0
   set   OEbar_I        to "000"
   set   D4_I           to "0"
   set   D4_O           to "0"
end vector

vector  D4_I_1
   set   OEbar_I        to "000"
   set   D4_I           to "1"
   set   D4_O           to "1"
end vector

vector  D5_I_0
   set   OEbar_I        to "000"
   set   D5_I           to "0"
   set   D5_O           to "0"
end vector

vector  D5_I_1
   set   OEbar_I        to "000"
   set   D5_I           to "1"
   set   D5_O           to "1"
end vector

vector  D6_I_0
   set   OEbar_I        to "000"
   set   D6_I           to "0"
   set   D6_O           to "0"
end vector

vector  D6_I_1
   set   OEbar_I        to "000"
   set   D6_I           to "1"
   set   D6_O           to "1"
end vector

vector  D7_I_0
   set   OEbar_I        to "000"
   set   D7_I           to "0"
   set   D7_O           to "0"
end vector

vector  D7_I_1
   set   OEbar_I        to "000"
   set   D7_I           to "1"
   set   D7_O           to "1"
end vector

!
!-----------------------------------------------------------------------
!

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit "awaretest D0 Test"
   execute  D0_I_0
   execute  D0_I_1
end unit

unit "awaretest D1 Test"
   execute  D1_I_0
   execute  D1_I_1
end unit

unit "awaretest D2 Test"
   execute  D2_I_0
   execute  D2_I_1
end unit

unit "awaretest D3 Test"
   execute  D3_I_0
   execute  D3_I_1
end unit

unit "awaretest D4 Test"
   execute  D4_I_0
   execute  D4_I_1
end unit

unit "awaretest D5 Test"
   execute  D5_I_0
   execute  D5_I_1
end unit

unit "awaretest D6 Test"
   execute  D6_I_0
   execute  D6_I_1
end unit

unit "awaretest D7 Test"
   execute  D7_I_0
   execute  D7_I_1
end unit


unit  "Test1 : Data Inputs"
   execute  DataIn_55
   execute  DataIn_AA
end unit

unit  "Test2 : Output Enable "
   execute  DataIn_55_Disabled_OE0
   execute  DataIn_55_Disabled_OE1
   execute  DataIn_55_Disabled_OE2
end unit

unit  "Test3 : Parity Check with Parity IN -Low"
   execute  DataIn_55_Parity_even
end unit

unit  "Test4 : Parity Check with Parity IN -High"
   execute  DataIn_55_Parity_odd
end unit

!
!  End of test
!