!!!!    6    0    1  991871979  V6d41                                         

! Device           : 4035
! Function         : shift_register totem 4-bit_parallel-in/out
! revision         : B.01.00
! safeguard        : standard_cmos
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

sequential

vector cycle 3u
receive delay 2.9u

assign  VDD         to pins 16
assign  VSS         to pins 8

assign  Parallel_inputs  to pins 9,10,11,12
assign  Serial_inputs    to pins 4,3
assign  J_input          to pins 4
assign  K_bar_input      to pins 3

assign  Outputs     to pins 1,15,14,13
assign  D0          to pins 13         !AT Added for minimum pin test.
assign  D1          to pins 14         !AT Added for minimum pin test.
assign  D2          to pins 15         !AT Added for minimum pin test.
assign  D3          to pins  1         !AT Added for minimum pin test.

assign  QD_output   to pins 13

assign  Clock       to pins 6
assign  Parallel_shift   to pins 7
assign  True_complement  to pins 2
assign  Clear       to pins 5

family  CMOS

power   VDD, VSS

inputs  Parallel_inputs, Serial_inputs, Clock, Parallel_shift
inputs  True_complement, Clear

outputs Outputs
outputs D0, D1, D2, D3          !AT Added for minimum pin test.

trace  Outputs to  Parallel_inputs, Serial_inputs, Clock
trace  Outputs to  Parallel_shift
trace  Outputs to  True_complement, Clear


!*********************************************************************
!*********************************************************************

vector    Clear_high
     set  Clock               to "0"
     set  True_complement     to "1"
     set  Clear               to "1"
     set  Outputs             to "0000"
end vector

vector    Clear_high_complement
     set  Clock               to "0"
     set  True_complement     to "0"
     set  Clear               to "1"
     set  Outputs             to "1111"
end vector

vector    Clock_high__parallel
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "1"
     set  Parallel_inputs     to "kkkk"
     set  Clock               to "1"
end vector

vector    Clock_high__serial
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "0"
     set  Serial_inputs       to "kk"
     set  Clock               to "1"
end vector

vector    Clock_high__shift
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "0"
     set  Clock               to "1"
end vector

vector    Clock_low
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
end vector

vector    Outputs_0000
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  Outputs             to "0000"
end vector

vector    Outputs_0010
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  Outputs             to "0010"
end vector
vector    Outputs_1001
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  Outputs             to "1001"
end vector
vector    Outputs_1101
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  Outputs             to "1101"
end vector
vector    Outputs_0110
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  Outputs             to "0110"
end vector

vector    Outputs_0000_ksd
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  Serial_inputs       to "kk"
     set  Outputs             to "0000"
end vector

vector    Outputs_0011
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  Outputs             to "0011"
end vector

vector    Outputs_0011_ksd
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  Serial_inputs       to "kk"
     set  Outputs             to "0011"
end vector

vector    Outputs_0101
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  Outputs             to "0101"
end vector

vector    Outputs_1010
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  Outputs             to "1010"
end vector

vector    Outputs_1100
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  Outputs             to "1100"
end vector

vector    Outputs_1100_ksd
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  Serial_inputs       to "kk"
     set  Outputs             to "1100"
end vector

vector    Outputs_1111
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  Outputs             to "1111"
end vector

vector    Outputs_1111_ksd
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  Serial_inputs       to "kk"
     set  Outputs             to "1111"
end vector

vector    Outputs_X001
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  Outputs             to "X001"
end vector

vector    Outputs_X010
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  Outputs             to "X010"
end vector

vector    Outputs_X101
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  Outputs             to "X101"
end vector

vector    Outputs_X110
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  Outputs             to "X110"
end vector

vector    Outputs_XX00
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  Outputs             to "XX00"
end vector

vector    Outputs_XX01
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  Outputs             to "XX01"
end vector

vector    Outputs_XX10
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  Outputs             to "XX10"
end vector

vector    Outputs_XX11
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  Outputs             to "XX11"
end vector

vector    Outputs_XXX0
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  Outputs             to "XXX0"
end vector

vector    Outputs_XXX1
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  Outputs             to "XXX1"
end vector

vector    Outputs_complement
     set  Clear               to "0"
     set  Clock               to "0"
     set  True_complement     to "0"
end vector

vector    Outputs_true
     set  Clear               to "0"
     set  Clock               to "0"
     set  True_complement     to "1"
end vector

vector    Parallel_inputs_0000
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "1"
     set  Clock               to "0"
     set  Parallel_inputs     to "0000"
end vector

vector    Parallel_inputs_0101
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "1"
     set  Clock               to "0"
     set  Parallel_inputs     to "0101"
end vector

vector    Parallel_inputs_1010
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "1"
     set  Clock               to "0"
     set  Parallel_inputs     to "1010"
end vector

vector    Parallel_inputs_1111
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "1"
     set  Clock               to "0"
     set  Parallel_inputs     to "1111"
end vector

vector    Parallel_shift_low
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Clock               to "0"
     set  Parallel_shift      to "0"
end vector

vector    Serial_inputs_00
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "0"
     set  Clock               to "0"
     set  Serial_inputs       to "00"
end vector

vector    Serial_inputs_01
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "0"
     set  Clock               to "0"
     set  Serial_inputs       to "01"
end vector

vector    Serial_inputs_10
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "0"
     set  Clock               to "0"
     set  Serial_inputs       to "10"
end vector

vector    Serial_inputs_11
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "0"
     set  Clock               to "0"
     set  Serial_inputs       to "11"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector    D0_0
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  D0                  to "0"
end vector

vector    D0_1
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  D0                  to "1"
end vector

vector    D1_0
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  D1                  to "0"
end vector

vector    D1_1
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  D1                  to "1"
end vector

vector    D2_0
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  D2                  to "0"
end vector

vector    D2_1
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  D2                  to "1"
end vector

vector    D3_0
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  D3                  to "0"
end vector

vector    D3_1
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  D3                  to "1"
end vector

vector    D0_0_ksd
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  Serial_inputs       to "kk"
     set  D0                  to "0"
end vector

vector    D0_1_ksd
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  Serial_inputs       to "kk"
     set  D0                  to "1"
end vector

vector    D1_0_ksd
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  Serial_inputs       to "kk"
     set  D1                  to "0"
end vector

vector    D1_1_ksd
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  Serial_inputs       to "kk"
     set  D1                  to "1"
end vector

vector    D2_0_ksd
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  Serial_inputs       to "kk"
     set  D2                  to "0"
end vector

vector    D2_1_ksd
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  Serial_inputs       to "kk"
     set  D2                  to "1"
end vector

vector    D3_0_ksd
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  Serial_inputs       to "kk"
     set  D3                  to "0"
end vector

vector    D3_1_ksd
     set  Clear               to "0"
     set  True_complement     to "k"
     set  Parallel_shift      to "k"
     set  Clock               to "0"
     set  Serial_inputs       to "kk"
     set  D3                  to "1"
end vector

!*********************************************************************
!*********************************************************************

sub  Clock_cycle (Clock_high)
     execute   Clock_high
     execute   Clock_low
end sub

!*********************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit "awaretest D0 serial input, true outputs Test"
     execute   Outputs_true
     execute   Serial_inputs_00
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_00
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_00
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_00
     call      Clock_cycle (Clock_high__serial)
     execute   D0_0_ksd

     execute   Outputs_true
     execute   Serial_inputs_11
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_11
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_11
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_11
     call      Clock_cycle (Clock_high__serial)
     execute   D0_1_ksd
end unit

unit "awaretest D1 serial input, true outputs Test"
     execute   Outputs_true
     execute   Serial_inputs_00
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_00
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_00
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_00
     call      Clock_cycle (Clock_high__serial)
     execute   D1_0_ksd

     execute   Outputs_true
     execute   Serial_inputs_11
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_11
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_11
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_11
     call      Clock_cycle (Clock_high__serial)
     execute   D1_1_ksd
end unit

unit "awaretest D2 serial input, true outputs Test"
     execute   Outputs_true
     execute   Serial_inputs_00
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_00
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_00
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_00
     call      Clock_cycle (Clock_high__serial)
     execute   D2_0_ksd

     execute   Outputs_true
     execute   Serial_inputs_11
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_11
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_11
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_11
     call      Clock_cycle (Clock_high__serial)
     execute   D2_1_ksd
end unit

unit "awaretest D3 serial input, true outputs Test"
     execute   Outputs_true
     execute   Serial_inputs_00
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_00
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_00
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_00
     call      Clock_cycle (Clock_high__serial)
     execute   D3_0_ksd

     execute   Outputs_true
     execute   Serial_inputs_11
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_11
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_11
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_11
     call      Clock_cycle (Clock_high__serial)
     execute   D3_1_ksd
end unit

unit "awaretest D0 parallel input and output only, true outputs Test"
     execute   Outputs_true
     execute   Parallel_inputs_0000
     call      Clock_cycle (Clock_high__parallel)
     execute   D0_0
     execute   Parallel_inputs_1111
     call      Clock_cycle (Clock_high__parallel)
     execute   D0_1
end unit

unit "awaretest D1 parallel input and output only, true outputs Test"
     execute   Outputs_true
     execute   Parallel_inputs_0000
     call      Clock_cycle (Clock_high__parallel)
     execute   D1_0
     execute   Parallel_inputs_1111
     call      Clock_cycle (Clock_high__parallel)
     execute   D1_1
end unit

unit "awaretest D2 parallel input and output only, true outputs Test"
     execute   Outputs_true
     execute   Parallel_inputs_0000
     call      Clock_cycle (Clock_high__parallel)
     execute   D2_0
     execute   Parallel_inputs_1111
     call      Clock_cycle (Clock_high__parallel)
     execute   D2_1
end unit

unit "awaretest D3 parallel input and output only, true outputs Test"
     execute   Outputs_true
     execute   Parallel_inputs_0000
     call      Clock_cycle (Clock_high__parallel)
     execute   D3_0
     execute   Parallel_inputs_1111
     call      Clock_cycle (Clock_high__parallel)
     execute   D3_1
end unit

unit "awaretest D0 serial input, inverted outputs Test"
     execute   Outputs_complement
     execute   Serial_inputs_00
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_00
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_00
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_00
     call      Clock_cycle (Clock_high__serial)
     execute   D0_1_ksd

     execute   Outputs_complement
     execute   Serial_inputs_11
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_11
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_11
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_11
     call      Clock_cycle (Clock_high__serial)
     execute   D0_0_ksd
end unit

unit "awaretest D1 serial input, inverted outputs Test"
     execute   Outputs_complement
     execute   Serial_inputs_00
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_00
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_00
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_00
     call      Clock_cycle (Clock_high__serial)
     execute   D1_1_ksd

     execute   Outputs_complement
     execute   Serial_inputs_11
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_11
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_11
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_11
     call      Clock_cycle (Clock_high__serial)
     execute   D1_0_ksd
end unit

unit "awaretest D2 serial input, inverted outputs Test"
     execute   Outputs_complement
     execute   Serial_inputs_00
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_00
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_00
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_00
     call      Clock_cycle (Clock_high__serial)
     execute   D2_1_ksd

     execute   Outputs_complement
     execute   Serial_inputs_11
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_11
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_11
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_11
     call      Clock_cycle (Clock_high__serial)
     execute   D2_0_ksd
end unit

unit "awaretest D3 serial input, inverted outputs Test"
     execute   Outputs_complement
     execute   Serial_inputs_00
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_00
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_00
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_00
     call      Clock_cycle (Clock_high__serial)
     execute   D3_1_ksd

     execute   Outputs_complement
     execute   Serial_inputs_11
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_11
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_11
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_11
     call      Clock_cycle (Clock_high__serial)
     execute   D3_0_ksd
end unit

unit "awaretest D0 parallel input and output only, inverted outputs Test"
     execute   Outputs_complement
     execute   Parallel_inputs_0000
     call      Clock_cycle (Clock_high__parallel)
     execute   D0_1
     execute   Parallel_inputs_1111
     call      Clock_cycle (Clock_high__parallel)
     execute   D0_0
end unit

unit "awaretest D1 parallel input and output only, inverted outputs Test"
     execute   Outputs_complement
     execute   Parallel_inputs_0000
     call      Clock_cycle (Clock_high__parallel)
     execute   D1_1
     execute   Parallel_inputs_1111
     call      Clock_cycle (Clock_high__parallel)
     execute   D1_0
end unit

unit "awaretest D2 parallel input and output only, inverted outputs Test"
     execute   Outputs_complement
     execute   Parallel_inputs_0000
     call      Clock_cycle (Clock_high__parallel)
     execute   D2_1
     execute   Parallel_inputs_1111
     call      Clock_cycle (Clock_high__parallel)
     execute   D2_0
end unit

unit "awaretest D3 parallel input and output only, inverted outputs Test"
     execute   Outputs_complement
     execute   Parallel_inputs_0000
     call      Clock_cycle (Clock_high__parallel)
     execute   D3_1
     execute   Parallel_inputs_1111
     call      Clock_cycle (Clock_high__parallel)
     execute   D3_0
end unit

!*********************************************************************

unit "serial input, true outputs"
     execute   Outputs_true
     execute   Serial_inputs_11
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_01
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_10
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_00
     call      Clock_cycle (Clock_high__serial)
     execute   Outputs_0011_ksd
     call      Clock_cycle (Clock_high__shift)
     execute   Outputs_X001
     call      Clock_cycle (Clock_high__shift)
     execute   Outputs_XX00
     call      Clock_cycle (Clock_high__shift)
     execute   Outputs_XXX0
end unit

unit "serial input, J tied to K_bar, true outputs"
     tied      J_input, K_bar_input
     execute   Outputs_true
     execute   Serial_inputs_11
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_11
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_00
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_00
     call      Clock_cycle (Clock_high__serial)
     execute   Outputs_0011
     call      Clock_cycle (Clock_high__shift)
     execute   Outputs_X001
     call      Clock_cycle (Clock_high__shift)
     execute   Outputs_XX00
     call      Clock_cycle (Clock_high__shift)
     execute   Outputs_XXX0
end unit

unit "parallel input, shift right, true outputs"
     execute   Outputs_true
     execute   Parallel_inputs_1010
     call      Clock_cycle (Clock_high__parallel)
     execute   Outputs_1010
     execute   Parallel_shift_low
     call      Clock_cycle (Clock_high__shift)
     execute   Outputs_X101
     call      Clock_cycle (Clock_high__shift)
     execute   Outputs_XX10
     call      Clock_cycle (Clock_high__shift)
     execute   Outputs_XXX1
     execute   Parallel_inputs_0101
     call      Clock_cycle (Clock_high__parallel)
     execute   Outputs_0101
     execute   Parallel_shift_low
     call      Clock_cycle (Clock_high__shift)
     execute   Outputs_X010
     call      Clock_cycle (Clock_high__shift)
     execute   Outputs_XX01
     call      Clock_cycle (Clock_high__shift)
     execute   Outputs_XXX0
end unit

unit "parallel input and output only, true outputs"
     execute   Outputs_true
     execute   Parallel_inputs_0000
     call      Clock_cycle (Clock_high__parallel)
     execute   Outputs_0000
     execute   Parallel_inputs_1111
     call      Clock_cycle (Clock_high__parallel)
     execute   Outputs_1111
end unit

unit "test clear, serial inputs, true outputs"
     execute   Outputs_true
     repeat    4 times
          execute   Serial_inputs_11
          call      Clock_cycle (Clock_high__serial)
     end repeat
     execute   Outputs_1111_ksd
     execute   Clear_high
end unit

unit "test clear, parallel inputs, true outputs"
     execute   Outputs_true
     execute   Parallel_inputs_1111
     call      Clock_cycle (Clock_high__parallel)
     execute   Outputs_1111
     execute   Clear_high
end unit

unit "circular shift, true outputs"
     tied      QD_output, Serial_inputs
     execute   Outputs_true
     execute   Parallel_inputs_1111
     call      Clock_cycle (Clock_high__parallel)
     execute   Outputs_1111
     execute   Parallel_inputs_1010
     call      Clock_cycle (Clock_high__parallel)
     execute   Parallel_shift_low
     repeat    2 times
          execute   Outputs_1010
          call      Clock_cycle (Clock_high__shift)
          execute   Outputs_0101
          call      Clock_cycle (Clock_high__shift)
     end repeat
     execute   Parallel_inputs_0101
     call      Clock_cycle (Clock_high__parallel)
     execute   Parallel_shift_low
     repeat    2 times
          execute   Outputs_0101
          call      Clock_cycle (Clock_high__shift)
          execute   Outputs_1010
          call      Clock_cycle (Clock_high__shift)
     end repeat
end unit

unit "serial input, inverted outputs"
     execute   Outputs_complement
     execute   Serial_inputs_11
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_01
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_10
     call      Clock_cycle (Clock_high__serial)
     execute   Serial_inputs_00
     call      Clock_cycle (Clock_high__serial)
     execute   Outputs_1100_ksd
     call      Clock_cycle (Clock_high__shift)
     execute   Outputs_X110
     call      Clock_cycle (Clock_high__shift)
     execute   Outputs_XX11
     call      Clock_cycle (Clock_high__shift)
     execute   Outputs_XXX1
end unit

unit "serial input, J tied to K_bar, inverted outputs"
     tied      J_input, K_bar_input
     execute   Outputs_complement
     repeat    2 times
          execute   Serial_inputs_11
          call      Clock_cycle (Clock_high__serial)
          execute   Serial_inputs_00
          call      Clock_cycle (Clock_high__serial)
     end repeat
     execute   Outputs_1010
     call      Clock_cycle (Clock_high__shift)
     execute   Outputs_X101
     call      Clock_cycle (Clock_high__shift)
     execute   Outputs_XX10
     call      Clock_cycle (Clock_high__shift)
     execute   Outputs_XXX1
end unit

unit "parallel input, shift right, inverted outputs"
     execute   Outputs_complement
     execute   Parallel_inputs_1010
     call      Clock_cycle (Clock_high__parallel)
     execute   Outputs_0101
     execute   Parallel_shift_low
     call      Clock_cycle (Clock_high__shift)
     execute   Outputs_X010
     call      Clock_cycle (Clock_high__shift)
     execute   Outputs_XX01
     call      Clock_cycle (Clock_high__shift)
     execute   Outputs_XXX0
     execute   Parallel_inputs_0101
     call      Clock_cycle (Clock_high__parallel)
     execute   Outputs_1010
     execute   Parallel_shift_low
     call      Clock_cycle (Clock_high__shift)
     execute   Outputs_X101
     call      Clock_cycle (Clock_high__shift)
     execute   Outputs_XX10
     call      Clock_cycle (Clock_high__shift)
     execute   Outputs_XXX1
end unit

unit "parallel input and output only, inverted outputs"
     execute   Outputs_complement
     execute   Parallel_inputs_0000
     call      Clock_cycle (Clock_high__parallel)
     execute   Outputs_1111
     execute   Parallel_inputs_1111
     call      Clock_cycle (Clock_high__parallel)
     execute   Outputs_0000
end unit

unit "test clear, serial inputs, inverted outputs"
     execute   Outputs_complement
     repeat    4 times
          execute   Serial_inputs_11
          call      Clock_cycle (Clock_high__serial)
     end repeat
     execute   Outputs_0000_ksd
     execute   Clear_high_complement
end unit

unit "test clear, parallel inputs, inverted outputs"
     execute   Outputs_complement
     execute   Parallel_inputs_1111
     call      Clock_cycle (Clock_high__parallel)
     execute   Outputs_0000
     execute   Clear_high_complement
end unit

unit "circular shift, inverted outputs"
     tied      QD_output, Serial_inputs
     execute   Outputs_complement
     execute   Parallel_inputs_1111
     call      Clock_cycle (Clock_high__parallel)
     execute   Outputs_0000
     execute   Parallel_inputs_1010
     call      Clock_cycle (Clock_high__parallel)
     execute   Parallel_shift_low
     execute   Outputs_0101
          call      Clock_cycle (Clock_high__shift)
          execute   Outputs_0010
          call      Clock_cycle (Clock_high__shift)
          execute   Outputs_1001
          call      Clock_cycle (Clock_high__shift)
     execute   Parallel_inputs_0101
     call      Clock_cycle (Clock_high__parallel)
     execute   Parallel_shift_low
          execute   Outputs_1010
          call      Clock_cycle (Clock_high__shift)
          execute   Outputs_1101
          call      Clock_cycle (Clock_high__shift)
          execute   Outputs_0110
          call      Clock_cycle (Clock_high__shift)
end unit

!    End of test