!!!!    6    0    1  989966201  Vb6c0                                         

! Device           : 27s281
! Function         : prom 3-state 1k x 8
! revision         : B.01.00
! safeguard        : standard_sttl
! Modifications    : Modified for AwareTest xi

sequential

receive delay 900n
vector cycle 1000n

warning"In order to test Chip Select (pin 24,25,26,28), pullups are"
warning"needed on Data_output (pin 12,13,14,17,19,20,21,22)."

assign  VCC         to pins 32
assign  GND         to pins 16

assign  Data_output to pins 22,21,20,19,17,14,13,12
assign  Data_D0     to pins 12   !AT Added for minimum pin test.
assign  Data_D1     to pins 13   !AT Added for minimum pin test.
assign  Data_D2     to pins 14   !AT Added for minimum pin test.
assign  Data_D3     to pins 17   !AT Added for minimum pin test.
assign  Data_D4     to pins 19   !AT Added for minimum pin test.
assign  Data_D5     to pins 20   !AT Added for minimum pin test.
assign  Data_D6     to pins 21   !AT Added for minimum pin test.
assign  Data_D7     to pins 22   !AT Added for minimum pin test.

assign  Address     to pins 29,30,3,4,5,6,7,8,9,10

assign  CS1bar      to pins 28
assign  CS2bar      to pins 26
assign  CS3         to pins 25
assign  CS4         to pins 24

assign  NC          to pins 1,2,11,15,18,23,27,31

nondigital   NC

family  TTL

power   VCC, GND

inputs  Address, CS1bar, CS2bar, CS3, CS4

outputs Data_output
outputs Data_D0, Data_D1, Data_D2, Data_D3 !AT Added for minimum pin test.
outputs Data_D4, Data_D5, Data_D6, Data_D7 !AT Added for minimum pin test.

disable Data_output  with CS1bar   to "1"
disable Data_output  with CS2bar   to "1"
disable Data_output  with CS3      to "0"
disable Data_output  with CS4      to "0"

when CS1bar is "1" inactive Data_output
when CS2bar is "1" inactive Data_output
when CS3    is "0" inactive Data_output
when CS4    is "0" inactive Data_output

trace Data_output to Address, CS1bar, CS2bar, CS3, CS4

!*********************************************************************
!*********************************************************************

vector    Count_vector
     set  CS1bar              to "0"
     set  CS2bar              to "0"
     set  CS3                 to "1"
     set  CS4                 to "1"
     set  Data_output         to "00000000"
     set  Address             to "0000000000"
     graycounter              Address
end vector

vector    CS1bar_false
     set  CS1bar              to "1"
     set  CS2bar              to "0"
     set  CS3                 to "1"
     set  CS4                 to "1"
     set  Data_output         to "11111111"
     set  Address             to "0000000000"
end vector

vector    CS2bar_false
     set  CS1bar              to "0"
     set  CS2bar              to "1"
     set  CS3                 to "1"
     set  CS4                 to "1"
     set  Data_output         to "11111111"
     set  Address             to "0000000000"
end vector

vector    CS3_false
     set  CS1bar              to "0"
     set  CS2bar              to "0"
     set  CS3                 to "0"
     set  CS4                 to "1"
     set  Data_output         to "11111111"
     set  Address             to "0000000000"
end vector

vector    CS4_false
     set  CS1bar              to "0"
     set  CS2bar              to "0"
     set  CS3                 to "1"
     set  CS4                 to "0"
     set  Data_output         to "11111111"
     set  Address             to "0000000000"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector    Count_vector_D0
     set  CS1bar              to "0"
     set  CS2bar              to "0"
     set  CS3                 to "1"
     set  CS4                 to "1"
     set  Data_D0             to "0"
     set  Address             to "0000000000"
     graycounter              Address
end vector

vector    Count_vector_D1
     set  CS1bar              to "0"
     set  CS2bar              to "0"
     set  CS3                 to "1"
     set  CS4                 to "1"
     set  Data_D1             to "0"
     set  Address             to "0000000000"
     graycounter              Address
end vector

vector    Count_vector_D2
     set  CS1bar              to "0"
     set  CS2bar              to "0"
     set  CS3                 to "1"
     set  CS4                 to "1"
     set  Data_D2             to "0"
     set  Address             to "0000000000"
     graycounter              Address
end vector

vector    Count_vector_D3
     set  CS1bar              to "0"
     set  CS2bar              to "0"
     set  CS3                 to "1"
     set  CS4                 to "1"
     set  Data_D3             to "0"
     set  Address             to "0000000000"
     graycounter              Address
end vector

vector    Count_vector_D4
     set  CS1bar              to "0"
     set  CS2bar              to "0"
     set  CS3                 to "1"
     set  CS4                 to "1"
     set  Data_D4             to "0"
     set  Address             to "0000000000"
     graycounter              Address
end vector

vector    Count_vector_D5
     set  CS1bar              to "0"
     set  CS2bar              to "0"
     set  CS3                 to "1"
     set  CS4                 to "1"
     set  Data_D5             to "0"
     set  Address             to "0000000000"
     graycounter              Address
end vector

vector    Count_vector_D6
     set  CS1bar              to "0"
     set  CS2bar              to "0"
     set  CS3                 to "1"
     set  CS4                 to "1"
     set  Data_D6             to "0"
     set  Address             to "0000000000"
     graycounter              Address
end vector

vector    Count_vector_D7
     set  CS1bar              to "0"
     set  CS2bar              to "0"
     set  CS3                 to "1"
     set  CS4                 to "1"
     set  Data_D7             to "0"
     set  Address             to "0000000000"
     graycounter              Address
end vector

!*********************************************************************
!*********************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit "awaretest D0 Test"
     preset counter      Count_vector_D0  compress
     repeat   255  times
          count     Count_vector_D0 compress
     end repeat
end unit

unit "awaretest D1 Test"
     preset counter      Count_vector_D1  compress
     repeat   255  times
          count     Count_vector_D1 compress
     end repeat
end unit

unit "awaretest D2 Test"
     preset counter      Count_vector_D2  compress
     repeat   255  times
          count     Count_vector_D2 compress
     end repeat
end unit

unit "awaretest D3 Test"
     preset counter      Count_vector_D3  compress
     repeat   255  times
          count     Count_vector_D3 compress
     end repeat
end unit

unit "awaretest D4 Test"
     preset counter      Count_vector_D4  compress
     repeat   255  times
          count     Count_vector_D4 compress
     end repeat
end unit

unit "awaretest D5 Test"
     preset counter      Count_vector_D5  compress
     repeat   255  times
          count     Count_vector_D5 compress
     end repeat
end unit

unit "awaretest D6 Test"
     preset counter      Count_vector_D6  compress
     repeat   255  times
          count     Count_vector_D6 compress
     end repeat
end unit

unit "awaretest D7 Test"
     preset counter      Count_vector_D7  compress
     repeat   255  times
          count     Count_vector_D7 compress
     end repeat
end unit

unit "ROM test"
     preset counter      Count_vector     compress
     repeat   2047 times
          count     Count_vector    compress
     end repeat
end unit

unit "chip select 1 test"
     execute CS1bar_false
end unit

unit "chip select 2 test"
     execute CS2bar_false
end unit

unit "chip select 3 test"
     execute CS3_false
end unit

unit "chip select 4 test"
     execute CS4_false
end unit

!    End of test