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W3622B ADS Core, EM Design, HSD Ckt Sim, Memory Designer
A cohesive memory design workflow for a predictive, productive, and insightful design journey
Starting from
For next-generation memory design and high-speed serial channel simulation.
Highlights
The W3622B ADS Core, EM Design, HSD Ckt Sim, Memory Designer includes:
- Memory Designer (including DDR Bus simulator)
- Via Designer
- Controlled Impedance Line Designer (CILD)
- Channel simulation
- Transient convolution
- EM Design enables the creation and import of parameterized 3D components into ADS
The W3622B is the standard bundle for high-speed serial channel simulation and next-generation memory design. HSD Circuit sim includes: S-parameter sim, Channel Sim, Transient sim, Controlled Impedance Line Designer (CILD), and Via Designer. CILD allows for accurate transmission line modeling. For SerDes and memory simulations, the ADS Memory Designer workflow enables a predictive and productive flow for next-generation memory designs.
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