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Highlights

Innovative solutions for identifying wire bond defects

The Keysight electrical structural tester is a capacitive-based testing solution designed to identify wire bond defects accurately. Leveraging the advanced part average test (PAT) analysis, the tester establishes a baseline from known-good units to swiftly detect deviations like near-shorts, stray wires, wire sweeps, and sags within integrated circuits (ICs). This capability ensures robust product quality management and significantly enhances manufacturing efficiency. The electrical structural tester enables you to:

  • Test single-die wire bonded packages in singulated or strip-based form factor.
  • Achieve high-volume production with up to 20 parallel test sites, achieving up to 72,000 IC units per hour (UPH).
  • Enhance yield through advanced methods like marginal retry test (MaRT), dynamic part averaging test (DPAT) and real-time part averaging test (RPAT).

Key Specifications

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Catch Wire Bond Defects Like Never Before

Top Stories and Key Events

Carol Leh featured interview with Digitimes

Carol Leh Discusses New Wire Bond Testing in SEMICON Taiwan Interview

Carol Leh, Senior Vice President of EISG, discussed why the Electrical Structural Tester marks a significant breakthrough for wire bond testing in the microelectronics industry during a featured interview with DIGITIMES. Watch the video to learn more.

How the Electrical Structural Tester Will Transform Wire Bond Testing: EE Times Asia Interview

In a featured interview by EE Times Asia, one of the Keysight representative explains how the Electrical Structural Tester will transform the wire bond testing industry. Watch the video or read the full story to learn more.

EE Times Asia Interview at SEMICON Taiwan 2024
s8050 software user interface with PAT algorithm

Spotting deviations with PAT

The electrical structural tester part average test (PAT) algorithm plays a crucial role in identifying abnormal wire bond variations that may indicate electrical or nonelectrical defects in ICs. The part average test uses continuous statistical analysis to monitor the production process, detecting deviations in part characteristics. The test employs dynamic PAT for strip testing and real-time PAT for singulated packages, ensuring the baseline of known good units for devices under test (DUTs) remains updated. This optimization adjusts test limits to minimize false rejects and scraps, reducing the need for retesting.

Capacitive Wire Bond Testing

The electrical structural tester brings cutting-edge wire bond testing with its Keysight vectorless test enhanced probe (VTEP) technology. This innovative approach uses capacitive coupling between metallic surfaces, such as wire bonds in an IC and a sensor plate above them. By injecting a stimulus through guard pins to reach the wire bond, the VTEP amplifier contacts the sensor plate, completing the circuit and capturing the coupling response. This process precisely pinpoints the wire bond's position beneath the metallic surface.

Advanced Capacitive Testing with Keysight VTEP
s8050 Electrical Structural Tester (EST)

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Featured Resources

Case Studies 2024.10.30

New Wire Bond Testing Solution Enhances Automotive IC Reliability

New Wire Bond Testing Solution Enhances Automotive IC Reliability

This success story highlights how Keysight’s capacitive-based Electrical Structural Tester (EST) enabled a top OSAT provider to eliminate wire bond defects in automotive ICs. By detecting hidden defects at high volumes, the solution reduced costly RMAs, enhanced reliability, and ensured the safety of automotive-grade ICs.

2024.10.30

White Papers 2024.08.15

Wire Bond Electrical Structural Test Methodologies

Wire Bond Electrical Structural Test Methodologies

Wire bonding, a foundational process in microelectronics, is essential for establishing a robust and low-resistance electrical connection between semiconductor chips and their respective packages or, in the case of multi-chip modules, between different chips. A connection is made from the bond pad on the chip to a corresponding pad on the package substrate or another chip through the meticulous bonding of a fine wire—usually composed of materials like gold, aluminum, or copper. This intricate process ensures the device's functionality, reliability, and overall performance. Several wire bonding testing methods have been developed and adopted to capture defects in molded integrated circuits (ICs) in microelectronics. However, the current testing methods on the market have their own strengths and weaknesses; they are not comprehensive but rather complement each other. An innovative method called capacitive testing has been developed to provide more comprehensive wire bond testing, detecting wire bond defects that are invisible with conventional testing methods. These defects include near shorts, wire sweep, wire sagging, and more.

2024.08.15

Data Sheets 2024.08.14

Electrical Structural Tester

Electrical Structural Tester

The Keysight Electrical Structural Tester is a cutting-edge solution designed to enhance defect detection in integrated circuit (IC) wire bonds using capacitive technology. It identifies various wire bond defects, including near-shorts, stray wires, wire sweep, and wire sags, helping to mitigate challenges posed by Electrical Overstress (EOS) on chip integrity. Optimized for production efficiency, the tester can support up to twenty parallel test sites, achieving a unit per hour (UPH) rate of 72,000 ICs, making it ideal for production-level testing processes and field return evaluations. This ensures manufacturers can produce high-quality components, reduce product returns, and maintain the reliability and consistency of electronic products.

2024.08.14

Product Fact Sheets 2024.08.14

Electrical Structural Tester

Electrical Structural Tester

The Keysight Electrical Structural Tester is a cutting-edge solution designed to enhance defect detection in integrated circuit (IC) wire bonds using capacitive technology. It identifies various wire bond defects, including near-shorts, stray wires, wire sweep, and wire sags, helping to mitigate challenges posed by Electrical Overstress (EOS) on chip integrity. Optimized for production efficiency, the tester can support up to twenty parallel test sites, achieving a Units Per Hour (UPH) rate of 72,000 ICs, making it ideal for production-level testing processes and field return evaluations. This ensures manufacturers can produce high-quality components, reduce product returns, and maintain the reliability and consistency of electronic products.

2024.08.14

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