ADS 2015.01 is the next major step in delivering product improvement and new capabilities to solve critical design challenges and improve design productivity through innovation, usability and design flow integration.

New W2309EP DDR Bus Simulator

The new W2309EP DDR Bus Simulator quickly generates accurate bit-error-rate (BER) contours, masks, and margins between the two, for the DDR memory bus specification published by JEDEC.

• Rigorous DQ and DQS eye calculations to arbitrarily low BER levels
• Built-in driver de-emphasis and receiver continuous-time-linear-equalizer models
• Mix-and-match between built-in, IBIS and circuit models of driver and receiver
• Accounts for crosstalk between signal lines
• Captures asymmetry between rise and fall edges
• Comprehensive margin measurements versus JEDEC DDR4 Rx mask at target BER
• Batch simulation for design space exploration and design of experiments
• Optional parameter sweeps on a compute cluster

Silicon RFIC Interoperability with Virtuoso

• Schematic Interoperable PDK support from GlobalFoundries, IBM, IHP & TowerJazz
• Express pcell support: Open Cadence Layouts in ADS. No PDK enablement is required

Figure 1. LNA design in IHP SGB25V interoperable PDK.

 Figure 2. Layout interoperability - Express Pcell example.

GoldenGate-in-ADS & New RFIC Cockpit

• RFIC designer’s favorite simulator in their favorite platform
• Capacity and performance benefits of the GoldenGate RFIC Simulation Software native in ADS, when using interoperable PDKs
• Proven Silicon RFIC simulator for larger-scale integrated RF circuit design
• Access to unique capabilities such as Fast Yield Contributor (FYC) analysis in ADS
• ADS RFIC Cockpit: Import simulation states from ADE or set up simulations directly in a familiar environment
• Interoperable RFIC design can be simulated with GoldenGate as well as with ADS simulator
• Design & simulate on Windows as well as Linux

Figure 3. NEW - "GoldenGate-in-ADS" is the RFIC designer's favorite simulator in their favorite platform.

Figure 4. Importing ADE simulation states using the ADS RFIC Cockpit helps with your migration. 

FEM Simulation Performance Improvements

• 2x faster “Out of the Box” performance
• Up to 16x faster with typical manual adjustments
• Improved efficiency for high number of ports

Layout & Layout Verification Improvements

• New Polymorphic Interconnect Modeling
• Layout interconnect design and editing usability improvements
• Refined layout toolbars and hotkey mapping
• DRC & LVS enhancements
• ODB++ import performance improvement
• Faster layout viewing and editing performance for large designs

Polymorphic Trace Interconnect Modeling

Figure 5. New Polymorphic Trace Interconnect Modeling.

Toolbars

Figure 6. Redefined layout toolbars in ADS.

Numerous Usability, Performance and Productivity Improvements

• Support for spaces in paths and file names
• Wireless Networking VTB enhanced with 802.11ad
  
• Distributed Computing enhanced for Harmonic Balance & Circuit Envelope, Channel & DDR Bus simulations
• W2317 DDR Bus Simulator 8-pack Element
• W2318 Channel Simulator 8-pack Element
• W2345 Harmonic Balance 8-pack Element
• W2346 Circuit Envelope 8-pack Element
• Redefined layout hotkey mapping

Layout Hot Keys

Figure 7. Redefined layout hotkey mapping.

Numerous Usability, Performance and Productivity Improvements

• Support for spaces in paths and file names
• Wireless Networking VTB enhanced with 802.11ad
• Distributed Computing enhanced for Harmonic Balance & Circuit Envelope, Channel & DDR Bus simulations
  • W2317 DDR Bus Simulator 8-pack Element
  • W2318 Channel Simulator 8-pack Element
  • W2345 Harmonic Balance 8-pack Element
  • W2346 Circuit Envelope 8-pack Element

View other ADS Product Versions.

Learn more about Keysight Advanced Design System (ADS)