!!!! 6 0 1 974732091 Vb255 ! Device : 7411245lcc ! Function : bus_transceiver 3-state non_inverting octal ! revision : B.01.00 ! safeguard : standard_acmos ! Modifications : Modified for AwareTest xi ! warning "This library has not been verified with hardware." combinatorial receive delay 900n vector cycle 1000n ! warning" This device has outputs that can be set to the high impedance" ! warning" state. In order to test Output Enable (pin 23), pullups are" ! warning" needed on outputs A1 and B2 (pin 9 and 5)." assign VCC to pins 2,28 assign GND to pins 13,14,16,17 assign E1_A to pins 9 assign E1_B to pins 6 assign E2_A to pins 10 assign E2_B to pins 5 assign E3_A to pins 11 assign E3_B to pins 4 assign E4_A to pins 12 assign E4_B to pins 3 assign E5_A to pins 18 assign E5_B to pins 27 assign E6_A to pins 19 assign E6_B to pins 26 assign E7_A to pins 20 assign E7_B to pins 25 assign E8_A to pins 21 assign E8_B to pins 24 assign All_A to pins 9,10,11,12,18,19,20,21 assign All_B to pins 6,5,4,3,27,26,25,24 assign Enable_bar to pins 23 assign Dir to pins 7 assign Disable to pins 23,7 assign NC to pins 1,8,15,22 nondigital NC family TTL power VCC, GND inputs Enable_bar, Dir bidirectional E1_A, E1_B, E2_A, E2_B, E3_A, E3_B, E4_A, E4_B bidirectional E5_A, E5_B, E6_A, E6_B, E7_A, E7_B, E8_A, E8_B bidirectional All_A, All_B when Enable_bar is "1" inactive All_A, All_B when Dir is "0" inputs All_B when Dir is "0" outputs All_A when Dir is "1" inputs All_A when Dir is "1" outputs All_B trace All_A, All_B to Enable_bar, Dir trace E1_A to E1_B trace E1_B to E1_A trace E2_A to E2_B trace E2_B to E2_A trace E3_A to E3_B trace E3_B to E3_A trace E4_A to E4_B trace E4_B to E4_A trace E5_A to E5_B trace E5_B to E5_A trace E6_A to E6_B trace E6_B to E6_A trace E7_A to E7_B trace E7_B to E7_A trace E8_A to E8_B trace E8_B to E8_A disable All_A, All_B with Enable_bar to "1" disable All_B with Dir to "0" disable All_A with Dir to "1" !********************************************************************* !********************************************************************* vector E1_A_hi drive All_A receive All_B set Dir to "1" set Enable_bar to "0" set E1_A to "1" set E1_B to "1" end vector vector E1_A_lo drive All_A receive All_B set Dir to "1" set Enable_bar to "0" set E1_A to "0" set E1_B to "0" end vector vector E2_A_hi drive All_A receive All_B set Dir to "1" set Enable_bar to "0" set E2_A to "1" set E2_B to "1" end vector vector E2_A_lo drive All_A receive All_B set Dir to "1" set Enable_bar to "0" set E2_A to "0" set E2_B to "0" end vector vector E3_A_hi drive All_A receive All_B set Dir to "1" set Enable_bar to "0" set E3_A to "1" set E3_B to "1" end vector vector E3_A_lo drive All_A receive All_B set Dir to "1" set Enable_bar to "0" set E3_A to "0" set E3_B to "0" end vector vector E4_A_hi drive All_A receive All_B set Dir to "1" set Enable_bar to "0" set E4_A to "1" set E4_B to "1" end vector vector E4_A_lo drive All_A receive All_B set Dir to "1" set Enable_bar to "0" set E4_A to "0" set E4_B to "0" end vector vector E5_A_hi drive All_A receive All_B set Dir to "1" set Enable_bar to "0" set E5_A to "1" set E5_B to "1" end vector vector E5_A_lo drive All_A receive All_B set Dir to "1" set Enable_bar to "0" set E5_A to "0" set E5_B to "0" end vector vector E6_A_hi drive All_A receive All_B set Dir to "1" set Enable_bar to "0" set E6_A to "1" set E6_B to "1" end vector vector E6_A_lo drive All_A receive All_B set Dir to "1" set Enable_bar to "0" set E6_A to "0" set E6_B to "0" end vector vector E7_A_hi drive All_A receive All_B set Dir to "1" set Enable_bar to "0" set E7_A to "1" set E7_B to "1" end vector vector E7_A_lo drive All_A receive All_B set Dir to "1" set Enable_bar to "0" set E7_A to "0" set E7_B to "0" end vector vector E8_A_hi drive All_A receive All_B set Dir to "1" set Enable_bar to "0" set E8_A to "1" set E8_B to "1" end vector vector E8_A_lo drive All_A receive All_B set Dir to "1" set Enable_bar to "0" set E8_A to "0" set E8_B to "0" end vector vector E1_B_hi drive All_B receive All_A set Dir to "0" set Enable_bar to "0" set E1_A to "1" set E1_B to "1" end vector vector E1_B_lo drive All_B receive All_A set Dir to "0" set Enable_bar to "0" set E1_A to "0" set E1_B to "0" end vector vector E2_B_hi drive All_B receive All_A set Dir to "0" set Enable_bar to "0" set E2_A to "1" set E2_B to "1" end vector vector E2_B_lo drive All_B receive All_A set Dir to "0" set Enable_bar to "0" set E2_A to "0" set E2_B to "0" end vector vector E3_B_hi drive All_B receive All_A set Dir to "0" set Enable_bar to "0" set E3_A to "1" set E3_B to "1" end vector vector E3_B_lo drive All_B receive All_A set Dir to "0" set Enable_bar to "0" set E3_A to "0" set E3_B to "0" end vector vector E4_B_hi drive All_B receive All_A set Dir to "0" set Enable_bar to "0" set E4_A to "1" set E4_B to "1" end vector vector E4_B_lo drive All_B receive All_A set Dir to "0" set Enable_bar to "0" set E4_A to "0" set E4_B to "0" end vector vector E5_B_hi drive All_B receive All_A set Dir to "0" set Enable_bar to "0" set E5_B to "1" set E5_A to "1" end vector vector E5_B_lo drive All_B receive All_A set Dir to "0" set Enable_bar to "0" set E5_B to "0" set E5_A to "0" end vector vector E6_B_hi drive All_B receive All_A set Dir to "0" set Enable_bar to "0" set E6_B to "1" set E6_A to "1" end vector vector E6_B_lo drive All_B receive All_A set Dir to "0" set Enable_bar to "0" set E6_B to "0" set E6_A to "0" end vector vector E7_B_hi drive All_B receive All_A set Dir to "0" set Enable_bar to "0" set E7_B to "1" set E7_A to "1" end vector vector E7_B_lo drive All_B receive All_A set Dir to "0" set Enable_bar to "0" set E7_B to "0" set E7_A to "0" end vector vector E8_B_hi drive All_B receive All_A set Dir to "0" set Enable_bar to "0" set E8_B to "1" set E8_A to "1" end vector vector E8_B_lo drive All_B receive All_A set Dir to "0" set Enable_bar to "0" set E8_B to "0" set E8_A to "0" end vector vector Disable_A_check_pullups drive All_B receive All_A set Dir to "0" set Enable_bar to "1" set E1_A to "1" set E1_B to "0" end vector vector Disable_B_check_pullups drive All_A receive All_B set Dir to "1" set Enable_bar to "1" set E2_A to "0" set E2_B to "1" end vector !********************************************************************* !********************************************************************* unit "awaretest E1 A in, B out" !AT Modified the unit name execute E1_A_lo execute E1_A_hi end unit !AT Added a new "end unit" unit "awaretest E2 A in, B out" !AT Added this unit execute E2_A_lo execute E2_A_hi end unit !AT Added a new "end unit" unit "awaretest E3 A in, B out" !AT Added this unit execute E3_A_lo execute E3_A_hi end unit !AT Added a new "end unit" unit "awaretest E4 A in, B out" !AT Added this unit execute E4_A_lo execute E4_A_hi end unit !AT Added a new "end unit" unit "awaretest E5 A in, B out" !AT Added this unit execute E5_A_lo execute E5_A_hi end unit !AT Added a new "end unit" unit "awaretest E6 A in, B out" !AT Added this unit execute E6_A_lo execute E6_A_hi end unit !AT Added a new "end unit" unit "awaretest E7 A in, B out" !AT Added this unit execute E7_A_lo execute E7_A_hi end unit !AT Added a new "end unit" unit "awaretest E8 A in, B out" !AT Added this unit execute E8_A_lo execute E8_A_hi end unit unit "awaretest E1 B in, A out" !AT Modified the unit name execute E1_B_lo execute E1_B_hi end unit !AT Added a new "end unit" unit "awaretest E2 B in, A out" !AT Added this unitA execute E2_B_lo execute E2_B_hi end unit !AT Added a new "end unit" unit "awaretest E3 B in, A out" !AT Added this unitA execute E3_B_lo execute E3_B_hi end unit !AT Added a new "end unit" unit "awaretest E4 B in, A out" !AT Added this unitA execute E4_B_lo execute E4_B_hi end unit !AT Added a new "end unit" unit "awaretest E5 B in, A out" !AT Added this unitA execute E5_B_lo execute E5_B_hi end unit !AT Added a new "end unit" unit "awaretest E6 B in, A out" !AT Added this unitA execute E6_B_lo execute E6_B_hi end unit !AT Added a new "end unit" unit "awaretest E7 B in, A out" !AT Added this unitA execute E7_B_lo execute E7_B_hi end unit !AT Added a new "end unit" unit "awaretest E8 B in, A out" !AT Added this unitA execute E8_B_lo execute E8_B_hi end unit unit "test Output enable" execute Disable_A_check_pullups execute Disable_B_check_pullups end unit ! End of test