N4916B De-Emphasis Signal Converter with Optional Clock Multiplier

Accurate Characterization of Multi-Gigabit Serial Interfaces Using Signal De-Emphasis

• adjustable de-emphasis for one pre- and two post-cursors of 0 to 12 dB
• supports data rates from 660 Mb/s to 14.2 Gb/s
• tolerates nonbalanced patterns
• transparent to jitter
• flexible use as front end for J-BERT N4903B, ParBERT 81250A, or other pattern generators
• optional clock multiplier (Option 001)
• small size
• programmable via J-BERT N4903B or standalone

Why Is Signal De-Emphasis Important?

The de-emphasis technique aids in the transmission of digital electrical signals at gigabit data rates. De-emphasis is a signal pre-distortion to compensate for signal degradations that occur when transmitting electrical signals with gigabit rates over PC board traces, backplanes, or long cables. The next generation of serial bus standards operating above 5 Gb/s will require sophisticated de-emphasis with multitap finite impulse response filtering.

High-speed digital interfaces such as PCI Express®, SATA, USB 3, QPI, and IEEE 802.3 backplanes (10GBASE-KR, 40GBASE-KR4) use de-emphasis.

What Does the N4916B Offer?

The Keysight N4916B de-emphasis signal converter enables R&D and test engineers to accurately emulate transmitter de-emphasis.

The N4916B can emulate transmitter de-emphasis with one pre- and two post-cursors and individually adjustable de-emphasis levels of up to 12.0 dB. With its DC coupling, it tolerates unbalanced pattern streams that often occur in training sequences. The N4916B is transparent to jitter when stimulated with jitter on data and clock signals, enabling emulation of real-world de-emphasis and jitter conditions that a receiver is expected to tolerate. De-emphasis can also compensate for distortions caused by cables, fixtures, or test boards in the test set for more precise device characterization results.

The de-emphasis signal converter can operate as a front end for J-BERT N4903B, ParBERT, or other gigabit pattern generators. Users can control it via a USB interface from the J-BERT N4903B user interface or a standalone user interface with programming examples.

What Does the N4916B's Clock-Multiplying Option Offer?

The clock multiplier option enables error counting and error analysis of devices using half-rate clocking. The full-rate clock is needed to use the error, eye, or jitter analysis capabilities of J-BERT N4903B.

Key Differences from Keysight's N4916A

• 3 adjustable cursors (N4916A has one post-cursor, sufficient for data rates < 5 Gb/s)
• optional clock multiplier
• standalone user interface
• maximum data rate
• aligned data and clock input signals required for full jitter transparency 
• size

PCIe is a trademark and PCI Express is a registered trademark of PCI-SIG.