Highlights

PathWave EP-Scan 2024 includes the following new features and major enhancements:

  • Improved visualization: See your board layout and nets in a 2D viewer 
  • Eye diagram generation: Provide a straightforward view of your signal integrity 
  • Components included in the simulation: Configure and analyze the nets connected by components

PathWave EP-Scan 2024 is available now.

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EP-Scan is the ultimate tool to empower your PCB design team, helping you confidently and quickly deliver high-quality, robust designs. Experience the future of PCB design with EP-Scan.

EP-Scan 2024

Your companion for PCB design teams

Signal integrity is the backbone of successful PCB designs. EP-Scan offers a user-friendly interface that streamlines your PCB design journey. With EP-Scan, you can:

  • Adjust stackup properties: Understand the impact of substrate stack-up properties on performance
  • Check against specifications: Apply specifications on impedance, return loss, and insertion loss to see a pass/fail evaluation
  • Identify layout issues: Spot potential concerns like via stubs and return path discontinuities
  • Create analysis report: Generate a report with simulation results and pass/fail status with one click 
  • Simplify design version simulation: Streamline simulation on revisions by eliminating setup time with the test plan feature

Will your DDR Trace Impedance Pass the Specification?

This demo uses EP-Scan to import the ODB++ (design for manufacturing format) and examine the DDR impedance values of an open-source board. After importing the ODB++ layout and configuring the substrate stack-up, it takes only 3 steps to verify whether the impedance of the nets passes the specification. The steps are:

  1. Select the nets
  2. Assign the nets and the 50-Ohm specification to a test plan
  3. Run the test plan

After the simulation is done, a simulation report is just one click away.

Featured Resources

Case Studies 2023.09.07

From Overwhelmed to Optimized: SECO's PCB Design Cycle Evolution

From Overwhelmed to Optimized: SECO's PCB Design Cycle Evolution

As the number of PCB designs at SECO rises, the signal integrity engineers who perform final verifications become overwhelmed. SECO integrated Keysight’s Electrical Performance Scan to optimize engineering resources, resulting in streamlined processes and a reported 25% increase in productivity. Delve into how SECO uses EP-Scan in this case study.

2023.09.07

Application Notes 2023.08.17

What is the Right Controlled Impedance for Your DDR5 Traces?

What is the Right Controlled Impedance for Your DDR5 Traces?

Starting with recognizing the lack of controlled impedance specification for DDR5 traces, this document delves into DDR vendor impedance recommendations, contrasts them with fabricated board data, and provides pragmatic design suggestions. Drawing from open-source DDR4 designs and reputable guides, this study demystifies impedance ranges for single-ended and differential traces, fostering informed DDR5 design decisions.

2023.08.17

Application Notes 2023.06.28

How to Verify Signal Integrity on a Work-in-progress USB4 PCB Design

How to Verify Signal Integrity on a Work-in-progress USB4 PCB Design

This document provides guidance on verifying signal integrity (SI) for a work-in-progress USB4 printed circuit board (PCB) design. It emphasizes the importance of early SI analysis to avoid costly design re-spins and delays in product release. The document outlines the need for impedance control and return loss management in USB4 designs. It offers recommendations for early SI verification, including impedance and loss reduction techniques. By following these guidelines and utilizing simulation tools, designers and engineers can ensure robust and reliable USB4 solutions, minimizing the risk of rework and delays.

2023.06.28

Application Notes 2023.04.28

How to Maximize Your Printed Circuit Board Design Productivity

How to Maximize Your Printed Circuit Board Design Productivity

2023.04.28

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