!!!! 6 0 1 991882813 Vba52 ! Device : 4021 ! Function : shift_register totem 8-bit_parallel-in_serial-in/out ! revision : B.01.00 ! safeguard : standard_cmos ! Modifications : Modified for AwareTest xi ! warning "This library has not been verified with hardware." sequential vector cycle 1.3u receive delay 1.2u assign VDD to pins 16 assign VSS to pins 8 assign Parallel_inputs to pins 7,6,5,4,13,14,15,1 assign Serial_input to pins 11 assign Outputs to pins 2,12,3 assign D0 to pins 3 !AT Added for minimum pin test. assign D1 to pins 12 !AT Added for minimum pin test. assign D2 to pins 2 !AT Added for minimum pin test. assign Q8_output to pins 3 assign Clock to pins 10 assign Input_control to pins 9 family CMOS power VDD, VSS inputs Parallel_inputs, Serial_input, Clock, Input_control outputs Outputs outputs D0, D1, D2 !AT Added for minimum pin test. trace Outputs to Parallel_inputs, Serial_input, Clock, Input_control !********************************************************************* !********************************************************************* vector Clock_high__serial set Serial_input to "k" set Input_control to "0" set Clock to "1" end vector vector Clock_high__shift set Input_control to "0" set Clock to "1" end vector vector Clock_low set Input_control to "k" set Clock to "0" end vector vector Input_control_high set Clock to "0" set Parallel_inputs to "kkkkkkkk" set Input_control to "1" end vector vector Input_control_low set Clock to "0" set Parallel_inputs to "kkkkkkkk" set Input_control to "0" end vector vector Outputs_010 set Input_control to "0" set Clock to "0" set Outputs to "010" end vector vector Outputs_010_ksd set Input_control to "0" set Clock to "0" set Serial_input to "k" set Outputs to "010" end vector vector Outputs_101 set Input_control to "0" set Clock to "0" set Outputs to "101" end vector vector Outputs_101_ksd set Input_control to "0" set Clock to "0" set Serial_input to "k" set Outputs to "101" end vector vector Outputs_X11 set Input_control to "0" set Clock to "0" set Outputs to "X11" end vector vector Outputs_XX1 set Input_control to "0" set Clock to "0" set Outputs to "XX1" end vector vector Outputs_X00 set Input_control to "0" set Clock to "0" set Outputs to "X00" end vector vector Outputs_XX0 set Input_control to "0" set Clock to "0" set Outputs to "XX0" end vector vector Outputs_100 set Input_control to "0" set Clock to "0" set Outputs to "100" end vector vector Outputs_110 set Input_control to "0" set Clock to "0" set Outputs to "110" end vector vector Outputs_011 set Input_control to "0" set Clock to "0" set Outputs to "011" end vector vector Outputs_001 set Input_control to "0" set Clock to "0" set Outputs to "001" end vector vector Parallel_inputs_00000000 set Clock to "0" set Input_control to "0" set Parallel_inputs to "00000000" end vector vector Parallel_inputs_11111111 set Clock to "0" set Input_control to "0" set Parallel_inputs to "11111111" end vector vector Parallel_inputs_00110011 set Clock to "0" set Input_control to "0" set Parallel_inputs to "00110011" end vector vector Parallel_inputs_11001100 set Clock to "0" set Input_control to "0" set Parallel_inputs to "11001100" end vector vector Serial_input_high set Clock to "0" set Input_control to "0" set Serial_input to "1" end vector vector Serial_input_low set Clock to "0" set Input_control to "0" set Serial_input to "0" end vector !AT The following vectors have been added for a minimum pins test. Any !AT vectors that references the data bus was copied and modified to reference !AT only a single pin of the data bus. vector D0_0 set Input_control to "0" set Clock to "0" set D0 to "0" end vector vector D0_1 set Input_control to "0" set Clock to "0" set D0 to "1" end vector vector D1_0 set Input_control to "0" set Clock to "0" set D1 to "0" end vector vector D1_1 set Input_control to "0" set Clock to "0" set D1 to "1" end vector vector D2_0 set Input_control to "0" set Clock to "0" set D2 to "0" end vector vector D2_1 set Input_control to "0" set Clock to "0" set D2 to "1" end vector vector D0_0_ksd set Input_control to "0" set Clock to "0" set Serial_input to "k" set D0 to "0" end vector vector D0_1_ksd set Input_control to "0" set Clock to "0" set Serial_input to "k" set D0 to "1" end vector vector D1_0_ksd set Input_control to "0" set Clock to "0" set Serial_input to "k" set D1 to "0" end vector vector D1_1_ksd set Input_control to "0" set Clock to "0" set Serial_input to "k" set D1 to "1" end vector vector D2_0_ksd set Input_control to "0" set Clock to "0" set Serial_input to "k" set D2 to "0" end vector vector D2_1_ksd set Input_control to "0" set Clock to "0" set Serial_input to "k" set D2 to "1" end vector !********************************************************************* !********************************************************************* sub Clock_cycle__serial execute Clock_high__serial execute Clock_low end sub sub Clock_cycle__shift execute Clock_high__shift execute Clock_low end sub !********************************************************************* !AT The following AwareTest units have been added for minimum pins tests. Each !AT unit tests a separate data pin starting with D0. unit "awaretest D0 serial input Test" repeat 8 times execute Serial_input_low call Clock_cycle__serial end repeat execute D0_0_ksd repeat 8 times execute Serial_input_high call Clock_cycle__serial end repeat execute D0_1_ksd end unit unit "awaretest D1 serial input Test" repeat 8 times execute Serial_input_low call Clock_cycle__serial end repeat execute D1_0_ksd repeat 8 times execute Serial_input_high call Clock_cycle__serial end repeat execute D1_1_ksd end unit unit "awaretest D2 serial input Test" repeat 8 times execute Serial_input_low call Clock_cycle__serial end repeat execute D2_0_ksd repeat 8 times execute Serial_input_high call Clock_cycle__serial end repeat execute D2_1_ksd end unit unit "awaretest D0 parallel input Test" execute Parallel_inputs_00000000 execute Input_control_high execute Input_control_low execute D0_0 execute Parallel_inputs_11111111 execute Input_control_high execute Input_control_low execute D0_1 end unit unit "awaretest D1 parallel input Test" execute Parallel_inputs_00000000 execute Input_control_high execute Input_control_low execute D1_0 execute Parallel_inputs_11111111 execute Input_control_high execute Input_control_low execute D1_1 end unit unit "awaretest D2 parallel input Test" execute Parallel_inputs_00000000 execute Input_control_high execute Input_control_low execute D2_0 execute Parallel_inputs_11111111 execute Input_control_high execute Input_control_low execute D2_1 end unit !********************************************************************* unit "test serial input" repeat 4 times execute Serial_input_high call Clock_cycle__serial execute Serial_input_low call Clock_cycle__serial end repeat execute Outputs_101_ksd call Clock_cycle__shift execute Outputs_010_ksd call Clock_cycle__shift execute Outputs_101_ksd end unit unit "test parallel input" execute Parallel_inputs_11001100 execute Input_control_high execute Input_control_low execute Outputs_100 call Clock_cycle__shift execute Outputs_110 call Clock_cycle__shift execute Outputs_011 call Clock_cycle__shift execute Outputs_001 call Clock_cycle__shift execute Outputs_100 call Clock_cycle__shift execute Outputs_110 call Clock_cycle__shift execute Outputs_X11 call Clock_cycle__shift execute Outputs_XX1 execute Parallel_inputs_00110011 execute Input_control_high execute Input_control_low execute Outputs_011 call Clock_cycle__shift execute Outputs_001 call Clock_cycle__shift execute Outputs_100 call Clock_cycle__shift execute Outputs_110 call Clock_cycle__shift execute Outputs_011 call Clock_cycle__shift execute Outputs_001 call Clock_cycle__shift execute Outputs_X00 call Clock_cycle__shift execute Outputs_XX0 end unit unit "circular shift, Q8 tied to serial input" tied Serial_input, Q8_output execute Parallel_inputs_11001100 execute Input_control_high execute Input_control_low execute Outputs_100 repeat 2 times call Clock_cycle__shift execute Outputs_110 call Clock_cycle__shift execute Outputs_011 call Clock_cycle__shift execute Outputs_001 call Clock_cycle__shift execute Outputs_100 end repeat execute Parallel_inputs_00110011 execute Input_control_high execute Input_control_low execute Outputs_011 repeat 2 times call Clock_cycle__shift execute Outputs_001 call Clock_cycle__shift execute Outputs_100 call Clock_cycle__shift execute Outputs_110 call Clock_cycle__shift execute Outputs_011 end repeat end unit ! End of test