!!!!    6    0    1  990220114  Vd6ec                                         

! Device           : 8T26
! Function         : quad three state bus transceiver
! revision         : B.01.00
! safeguard        : standard_ttl
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

combinatorial

assign VCC                  to pins 16
assign GND                  to pins 8

assign Receiver_Outputs     to pins 2,5,11,14
assign RO1                  to pins 2
assign RO2                  to pins 5
assign RO3                  to pins 11
assign RO4                  to pins 14

assign Driver_Inputs        to pins 4,7,9,12
assign DI1                  to pins 4
assign DI2                  to pins 7
assign DI3                  to pins 9
assign DI4                  to pins 12

assign Bus                  to pins 3,6,10,13
assign B1                   to pins 3
assign B2                   to pins 6
assign B3                   to pins 10
assign B4                   to pins 13

assign Receiver_Enable_bar  to pins 1
assign Driver_Enable        to pins 15

power VCC, GND

family TTL

inputs Driver_Inputs,Receiver_Enable_bar,Driver_Enable
inputs DI1, DI2, DI3, DI4     !AT Added for minimum pin test.

outputs Receiver_Outputs
outputs RO1, RO2, RO3, RO4    !AT Added for minimum pin test.

bidirectional Bus
bidirectional B1, B2, B3, B4  !AT Added for minimum pin test.

disable Receiver_Outputs with Receiver_Enable_bar to "1"

disable Bus with Driver_Enable to "0"

when Receiver_Enable_bar is "1" inactive Receiver_Outputs
when Driver_Enable is "0" inputs Bus
when Driver_Enable is "1" outputs Bus

trace RO1 to DI1, B1, Receiver_Enable_bar, Driver_Enable
trace RO2 to DI2, B2, Receiver_Enable_bar, Driver_Enable
trace RO3 to DI3, B3, Receiver_Enable_bar, Driver_Enable
trace RO4 to DI4, B4, Receiver_Enable_bar, Driver_Enable

trace B1 to DI1, Driver_Enable
trace B2 to DI2, Driver_Enable
trace B3 to DI3, Driver_Enable
trace B4 to DI4, Driver_Enable

!*******************************************************************************
!*******************************************************************************


vector     Recv_bus_Control
     set   Driver_Enable        to  "1"
end vector

vector     Drive_bus_Control
     set   Receiver_Enable_bar  to  "0"
     set   Driver_Enable        to  "0"
end vector

vector     Recv_Disabled
     set   Receiver_Enable_bar  to  "1"
     set   Driver_Enable        to  "0"
end vector

vector     Drive_bus_1111_Recv_Disabled
     initialize to Recv_Disabled
     drive           Bus
     set   Bus   to  "1111"
     set   Receiver_Outputs   to  "1111"
end vector

vector     Drive_bus_0000
     initialize to Drive_Bus_Control
     drive           Bus
     set   Bus   to  "0000"
     set   Receiver_Outputs   to  "1111"
end vector

vector     Drive_bus_1111
     initialize to Drive_Bus_Control
     drive           Bus
     set   Bus   to  "1111"
     set   Receiver_Outputs   to  "0000"
end vector

vector     Drive_bus_1110
     initialize to Drive_Bus_Control
     drive           Bus
     set   Bus   to  "1110"
     set   Receiver_Outputs   to  "0001"
end vector

vector     Drive_bus_1101
     initialize to Drive_Bus_Control
     drive           Bus
     set   Receiver_Outputs   to  "0010"
     set   Bus   to  "1101"
end vector

vector     Drive_bus_1011
     initialize to Drive_Bus_Control
     drive           Bus
     set   Bus   to  "1011"
     set   Receiver_Outputs   to  "0100"
end vector

vector     Drive_bus_0111
     initialize to Drive_Bus_Control
     drive           Bus
     set   Bus   to  "0111"
     set   Receiver_Outputs   to  "1000"
end vector


vector     Drive_inputs_1111
     initialize to Recv_bus_Control
     receive           Bus
     set   Driver_Inputs   to  "1111"
     set   Bus   to  "0000"
end vector

vector     Drive_inputs_1110
     initialize to Recv_bus_Control
     receive           Bus
     set   Driver_Inputs   to  "1110"
     set   Bus   to  "0001"
end vector

vector     Drive_inputs_1101
     initialize to Recv_bus_Control
     receive           Bus
     set   Driver_Inputs   to  "1101"
     set   Bus   to  "0010"
end vector

vector     Drive_inputs_1011
     initialize to Recv_bus_Control
     receive           Bus
     set   Driver_Inputs   to  "1011"
     set   Bus   to  "0100"
end vector

vector     Drive_inputs_0111
     initialize to Recv_bus_Control
     receive           Bus
     set   Driver_Inputs   to  "0111"
     set   Bus   to  "1000"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector     Drive_bus_B1_1_RO1_0
     initialize to Drive_Bus_Control
     drive           B1
     set   B1                 to  "1"
     set   RO1                to  "0"
end vector

vector     Drive_bus_B1_0_RO1_1
     initialize to Drive_Bus_Control
     drive           B1
     set   B1                 to  "0"
     set   RO1                to  "1"
end vector

vector     Drive_bus_B2_1_RO2_0
     initialize to Drive_Bus_Control
     drive           B2
     set   B2                 to  "1"
     set   RO2                to  "0"
end vector

vector     Drive_bus_B2_0_RO2_1
     initialize to Drive_Bus_Control
     drive           B2
     set   B2                 to  "0"
     set   RO2                to  "1"
end vector

vector     Drive_bus_B3_1_RO3_0
     initialize to Drive_Bus_Control
     drive           B3
     set   B3                 to  "1"
     set   RO3                to  "0"
end vector

vector     Drive_bus_B3_0_RO3_1
     initialize to Drive_Bus_Control
     drive           B3
     set   B3                 to  "0"
     set   RO3                to  "1"
end vector

vector     Drive_bus_B4_1_RO4_0
     initialize to Drive_Bus_Control
     drive           B4
     set   B4                 to  "1"
     set   RO4                to  "0"
end vector

vector     Drive_bus_B4_0_RO4_1
     initialize to Drive_Bus_Control
     drive           B4
     set   B4                 to  "0"
     set   RO4                to  "1"
end vector

vector     Drive_inputs_DI1_1_B1_0
     initialize to Recv_bus_Control
     receive         B1
     set   DI1                to  "1"
     set   B1                 to  "0"
end vector

vector     Drive_inputs_DI1_0_B1_1
     initialize to Recv_bus_Control
     receive         B1
     set   DI1                to  "0"
     set   B1                 to  "1"
end vector

vector     Drive_inputs_DI2_1_B2_0
     initialize to Recv_bus_Control
     receive         B2
     set   DI2                to  "1"
     set   B2                 to  "0"
end vector

vector     Drive_inputs_DI2_0_B2_1
     initialize to Recv_bus_Control
     receive         B2
     set   DI2                to  "0"
     set   B2                 to  "1"
end vector

vector     Drive_inputs_DI3_1_B3_0
     initialize to Recv_bus_Control
     receive         B3
     set   DI3                to  "1"
     set   B3                 to  "0"
end vector

vector     Drive_inputs_DI3_0_B3_1
     initialize to Recv_bus_Control
     receive         B3
     set   DI3                to  "0"
     set   B3                 to  "1"
end vector

vector     Drive_inputs_DI4_1_B4_0
     initialize to Recv_bus_Control
     receive         B4
     set   DI4                to  "1"
     set   B4                 to  "0"
end vector

vector     Drive_inputs_DI4_0_B4_1
     initialize to Recv_bus_Control
     receive         B4
     set   DI4                to  "0"
     set   B4                 to  "1"
end vector

!*******************************************************************************
!*******************************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with B1.

unit "awaretest Data B1 Input - Receiver Output RO1 Test"
    execute     Drive_bus_B1_1_RO1_0
    execute     Drive_bus_B1_0_RO1_1
end unit

unit "awaretest Data B2 Input - Receiver Output RO2 Test"
    execute     Drive_bus_B2_1_RO2_0
    execute     Drive_bus_B2_0_RO2_1
end unit

unit "awaretest Data B3 Input - Receiver Output RO3 Test"
    execute     Drive_bus_B3_1_RO3_0
    execute     Drive_bus_B3_0_RO3_1
end unit

unit "awaretest Data B4 Input - Receiver Output RO4 Test"
    execute     Drive_bus_B4_1_RO4_0
    execute     Drive_bus_B4_0_RO4_1
end unit

unit "awaretest Drive Input DI1 - Data B1 Output Test"
    execute     Drive_inputs_DI1_1_B1_0
    execute     Drive_inputs_DI1_0_B1_1
end unit

unit "awaretest Drive Input DI2 - Data B2 Output Test"
    execute     Drive_inputs_DI2_1_B2_0
    execute     Drive_inputs_DI2_0_B2_1
end unit

unit "awaretest Drive Input DI3 - Data B3 Output Test"
    execute     Drive_inputs_DI3_1_B3_0
    execute     Drive_inputs_DI3_0_B3_1
end unit

unit "awaretest Drive Input DI4 - Data B4 Output Test"
    execute     Drive_inputs_DI4_1_B4_0
    execute     Drive_inputs_DI4_0_B4_1
end unit

! The first unit drives the driver inputs and receives the pattern on the
! data bus. The second unit drives the data bus and receives the pattern
! on the receiver outputs.

unit   "Drive Bus To Receiver Outputs"
    execute   Drive_bus_1111
    execute   Drive_bus_1110
    execute   Drive_bus_1101
    execute   Drive_bus_1011
    execute   Drive_bus_0111
end unit

unit    "Drive Inputs To Data Bus"
    execute   Drive_inputs_1111
    execute   Drive_inputs_1110
    execute   Drive_inputs_1101
    execute   Drive_inputs_1011
    execute   Drive_inputs_0111
end unit

unit "Test Receiver Enable"
    execute   Drive_bus_0000
    execute   Drive_bus_1111_Recv_Disabled
end unit

!  End Of Test