!!!! 6 0 1 719003989 0000 !----------------------------------------------------------------------- ! Copyright (c) Hewlett-Packard Co. 1992 ! ! All Rights Reserved. Reproduction, adaptation, or translation ! without prior written permission is prohibited, except as allowed ! under the copyright laws. ! !----------------------------------------------------------------------- ! ! Device: pcf8571 ! Manufacturer: VALVO ! Description: 128 * 8 bit static ram I^2C -Bus ! Package: 8 pin DIL ! Test Platform: 3065,3070 ! Safeguard: standard_cmos ! !----------------------------------------------------------------------- ! ! Additional Comments: ! !----------------------------------------------------------------------- vector cycle 1000n receive delay 900n assign VCC to pins 8 assign GND to pins 4 assign A0 to pins 1 default "0" assign A1 to pins 2 default "0" assign A2 to pins 3 default "0" assign Test to pins 7 default "0" assign SCL to pins 6 assign SDA to pins 5 family TTL power VCC,GND inputs A0,A1,A2,SCL,TEST bidirectional SDA disable SDA with SCL to "1" warning " pull-ups required on SDA + SDC ! " warning " Test for A0=0 A1=0 A2=0 !" ! ****************************************************************************** ! VECTORS ! ****************************************************************************** vector Begin drive SDA set SCL to "1" set SDA to "1" end vector vector Start drive SDA set SCL to "1" set SDA to "0" end vector vector Stop drive SDA set SCL to "1" set SDA to "1" end vector vector SCL_0 drive SDA set SCL to "0" set SDA to "k" end vector vector SCL_1 drive SDA set SCL to "1" set SDA to "k" end vector vector Dd_0 drive SDA set SCL to "k" set SDA to "0" end vector vector Dd_1 drive SDA set SCL to "k" set SDA to "1" end vector vector SCL_0_D_X receive SDA set SCL to "0" set SDA to "x" end vector vector SCL_1_D_X receive SDA set SCL to "1" set SDA to "x" end vector vector ACK_S0 receive SDA set SCL to "1" set SDA to "0" end vector vector SCL_R_0 receive SDA set SCL to "0" set SDA to "x" end vector vector SCL_R_1 receive SDA set SCL to "1" set SDA to "x" end vector vector Dr_0 receive SDA set SCL to "k" set SDA to "0" end vector vector Dr_1 receive SDA set SCL to "k" set SDA to "1" end vector vector ACK_M0 drive SDA set SCL to "k" set SDA to "0" end vector vector ACK_M1 receive SDA set SCL to "k" set SDA to "1" end vector vector RW_0 drive SDA set SCL to "k" set SDA to "0" end vector vector RW_1 drive SDA set SCL to "k" set SDA to "1" end vector vector SCL_1_D_0 drive SDA set SCL to "1" set SDA to "0" end vector ! ****************************************************************************** ! SUBS ! ****************************************************************************** sub IC_Address(RW) execute SCL_0 execute Dd_1 execute SCL_1 execute SCL_0 execute Dd_0 execute SCL_1 execute SCL_0 execute Dd_1 execute SCL_1 execute SCL_0 execute Dd_0 execute SCL_1 execute SCL_0 execute Dd_0 execute SCL_1 execute SCL_0 execute Dd_0 execute SCL_1 execute SCL_0 execute Dd_0 execute SCL_1 execute SCL_0 execute RW execute SCL_1 execute SCL_0_D_X execute SCL_1_D_X execute Ack_S0 !ACK von Slave execute SCL_0_D_X end sub sub Word_Address(D0,D1,D2,D3,D4,D5,D6,D7) execute D0 execute SCL_1 execute SCL_0 execute D1 execute SCL_1 execute SCL_0 execute D2 execute SCL_1 execute SCL_0 execute D3 execute SCL_1 execute SCL_0 execute D4 execute SCL_1 execute SCL_0 execute D5 execute SCL_1 execute SCL_0 execute D6 execute SCL_1 execute SCL_0 execute D7 execute SCL_1 execute SCL_0_D_X execute SCL_1_D_X execute ACK_S0 !Ack von Slave execute SCL_0_D_X end sub sub Write_Data(D0,D1,D2,D3,D4,D5,D6,D7) execute D0 execute SCL_1 execute SCL_0 execute D1 execute SCL_1 execute SCL_0 execute D2 execute SCL_1 execute SCL_0 execute D3 execute SCL_1 execute SCL_0 execute D4 execute SCL_1 execute SCL_0 execute D5 execute SCL_1 execute SCL_0 execute D6 execute SCL_1 execute SCL_0 execute D7 execute SCL_1 execute SCL_0_D_X execute SCL_1_D_X execute ACK_S0 !Ack von Slave execute SCL_0_D_X end sub sub Read_Data(D0,D1,D2,D3,D4,D5,D6,D7) execute SCL_R_1 execute D0 execute SCL_R_0 execute SCL_R_1 execute D1 execute SCL_R_0 execute SCL_R_1 execute D2 execute SCL_R_0 execute SCL_R_1 execute D3 execute SCL_R_0 execute SCL_R_1 execute D4 execute SCL_R_0 execute SCL_R_1 execute D5 execute SCL_R_0 execute SCL_R_1 execute D6 execute SCL_R_0 execute SCL_R_1 execute D7 execute SCL_0_D_X execute ACK_M0 !Ack von Master execute SCL_1_D_0 execute SCL_0_D_X end sub sub Read_Data_Last(D0,D1,D2,D3,D4,D5,D6,D7) execute SCL_R_1 execute D0 execute SCL_R_0 execute SCL_R_1 execute D1 execute SCL_R_0 execute SCL_R_1 execute D2 execute SCL_R_0 execute SCL_R_1 execute D3 execute SCL_R_0 execute SCL_R_1 execute D4 execute SCL_R_0 execute SCL_R_1 execute D5 execute SCL_R_0 execute SCL_R_1 execute D6 execute SCL_R_0 execute SCL_R_1 execute D7 execute SCL_0_D_X execute SCL_1_D_X execute ACK_M1 ! kein Ack von Master ACK = 1 execute SCL_0_D_X end sub ! ****************************************************************************** ! UNITS ! ****************************************************************************** unit "write" execute Begin ! c=1 d=1 ! execute Start ! c=1 d=0 execute Stop ! c=1 d=1 execute Start ! c=1 d=0 call IC_Address(RW_0) call Word_Address(Dd_0,Dd_0,Dd_0,Dd_0,Dd_0,Dd_0,Dd_0,Dd_0) repeat 64 times call Write_Data(Dd_1,Dd_0,Dd_1,Dd_0,Dd_1,Dd_0,Dd_1,Dd_0) call Write_Data(Dd_0,Dd_1,Dd_0,Dd_1,Dd_0,Dd_1,Dd_0,Dd_1) end repeat execute Stop end unit unit "read" execute Begin execute Start execute Stop execute Start call IC_Address(RW_0) call Word_Address(Dd_0,Dd_0,Dd_0,Dd_0,Dd_0,Dd_0,Dd_0,Dd_0) execute Begin sync execute Start call IC_Address(RW_1) repeat 63 times !ACK = 0 call Read_Data(Dr_1,Dr_0,Dr_1,Dr_0,Dr_1,Dr_0,Dr_1,Dr_0) ! "" call Read_Data(Dr_0,Dr_1,Dr_0,Dr_1,Dr_0,Dr_1,Dr_0,Dr_1) ! "" end repeat call Read_Data(Dr_1,Dr_0,Dr_1,Dr_0,Dr_1,Dr_0,Dr_1,Dr_0) ! "" call Read_Data_last(Dr_0,Dr_1,Dr_0,Dr_1,Dr_0,Dr_1,Dr_0,Dr_1) !ACK = 1 execute Stop end unit ! ! End of test !