!!!! 6 0 1 986331125 V94dd
! Device : 74ls319
! Function : Static RAM oc 16 x 4
! revision : B.01.00
! safeguard : hi_oc_lsttl
! Modifications : Modified for AwareTest xi
!
warning "This library has not been verified with hardware."
vector cycle 2u
receive delay 1.9u
! warning "Pull-ups are required on open-collector outputs."
assign VCC to pins 16
assign GND to pins 8
assign Address to pins 13,14,15,1
assign Data_in to pins 12,10,6,4
assign D4 to pins 12
assign D3 to pins 10
assign D2 to pins 6
assign D1 to pins 4
assign Data_out to pins 11,9,7,5
assign Q4 to pins 11
assign Q3 to pins 9
assign Q2 to pins 7
assign Q1 to pins 5
assign Chip_Select_bar to pins 2
assign Write_bar to pins 3
assign Disables to pins 2,3
power VCC, GND
family TTL
inputs Address, Data_in, Chip_Select_bar, Write_bar, Disables
inputs D1, D2, D3, D4 !AT Added for minimum pin test.
outputs Data_out
outputs Q1, Q2, Q3, Q4 !AT Added for minimum pin test.
disable Data_out with Disables to "00"
disable Data_out with Disables to "1X"
when Chip_Select_bar is "1" inactive Data_out
trace Q4 to Address, D4, Chip_Select_bar, Write_bar, Disables
trace Q3 to Address, D3, Chip_Select_bar, Write_bar, Disables
trace Q2 to Address, D2, Chip_Select_bar, Write_bar, Disables
trace Q1 to Address, D1, Chip_Select_bar, Write_bar, Disables
set load on groups Data_out to pull up
!*****************************************************************************
!*****************************************************************************
vector Address_0000
set Address to "0000"
set Chip_Select_bar to "0"
set Write_bar to "1"
end vector
vector Address_0001
set Address to "0001"
set Chip_Select_bar to "0"
set Write_bar to "1"
end vector
vector Address_0011
set Address to "0011"
set Chip_Select_bar to "0"
set Write_bar to "1"
end vector
vector Address_0111
set Address to "0111"
set Chip_Select_bar to "0"
set Write_bar to "1"
end vector
vector Address_1111
set Address to "1111"
set Chip_Select_bar to "0"
set Write_bar to "1"
end vector
vector Data_in_0000
set Address to "kkkk"
set Data_in to "0000"
set Chip_Select_bar to "0"
set Write_bar to "0"
end vector
vector Data_in_0001
set Address to "kkkk"
set Data_in to "0001"
set Chip_Select_bar to "0"
set Write_bar to "0"
end vector
vector Data_in_0011
set Address to "kkkk"
set Data_in to "0011"
set Chip_Select_bar to "0"
set Write_bar to "0"
end vector
vector Data_in_0111
set Address to "kkkk"
set Data_in to "0111"
set Chip_Select_bar to "0"
set Write_bar to "0"
end vector
vector Data_in_1111
set Address to "kkkk"
set Data_in to "1111"
set Chip_Select_bar to "0"
set Write_bar to "0"
end vector
vector End_Write
set Data_in to "kkkk"
set Chip_Select_bar to "0"
set Write_bar to "1"
end vector
vector End_Cycle
set Chip_Select_bar to "1"
set Write_bar to "1"
end vector
vector Data_out_0000
set Address to "kkkk"
set Chip_Select_bar to "0"
set Write_bar to "1"
set Data_out to "0000"
end vector
vector Data_out_0001
set Address to "kkkk"
set Chip_Select_bar to "0"
set Write_bar to "1"
set Data_out to "0001"
end vector
vector Data_out_0011
set Address to "kkkk"
set Chip_Select_bar to "0"
set Write_bar to "1"
set Data_out to "0011"
end vector
vector Data_out_0111
set Address to "kkkk"
set Chip_Select_bar to "0"
set Write_bar to "1"
set Data_out to "0111"
end vector
vector Data_out_1111
set Address to "kkkk"
set Chip_Select_bar to "0"
set Write_bar to "1"
set Data_out to "1111"
end vector
!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.
vector Data_in_D1_0
set Address to "kkkk"
set D1 to "0"
set Chip_Select_bar to "0"
set Write_bar to "0"
end vector
vector Data_in_D1_1
set Address to "kkkk"
set D1 to "1"
set Chip_Select_bar to "0"
set Write_bar to "0"
end vector
vector Data_in_D2_0
set Address to "kkkk"
set D2 to "0"
set Chip_Select_bar to "0"
set Write_bar to "0"
end vector
vector Data_in_D2_1
set Address to "kkkk"
set D2 to "1"
set Chip_Select_bar to "0"
set Write_bar to "0"
end vector
vector Data_in_D3_0
set Address to "kkkk"
set D3 to "0"
set Chip_Select_bar to "0"
set Write_bar to "0"
end vector
vector Data_in_D3_1
set Address to "kkkk"
set D3 to "1"
set Chip_Select_bar to "0"
set Write_bar to "0"
end vector
vector Data_in_D4_0
set Address to "kkkk"
set D4 to "0"
set Chip_Select_bar to "0"
set Write_bar to "0"
end vector
vector Data_in_D4_1
set Address to "kkkk"
set D4 to "1"
set Chip_Select_bar to "0"
set Write_bar to "0"
end vector
vector Data_out_Q1_0
set Address to "kkkk"
set Chip_Select_bar to "0"
set Write_bar to "1"
set Q1 to "0"
end vector
vector Data_out_Q1_1
set Address to "kkkk"
set Chip_Select_bar to "0"
set Write_bar to "1"
set Q1 to "1"
end vector
vector Data_out_Q2_0
set Address to "kkkk"
set Chip_Select_bar to "0"
set Write_bar to "1"
set Q2 to "0"
end vector
vector Data_out_Q2_1
set Address to "kkkk"
set Chip_Select_bar to "0"
set Write_bar to "1"
set Q2 to "1"
end vector
vector Data_out_Q3_0
set Address to "kkkk"
set Chip_Select_bar to "0"
set Write_bar to "1"
set Q3 to "0"
end vector
vector Data_out_Q3_1
set Address to "kkkk"
set Chip_Select_bar to "0"
set Write_bar to "1"
set Q3 to "1"
end vector
vector Data_out_Q4_0
set Address to "kkkk"
set Chip_Select_bar to "0"
set Write_bar to "1"
set Q4 to "0"
end vector
vector Data_out_Q4_1
set Address to "kkkk"
set Chip_Select_bar to "0"
set Write_bar to "1"
set Q4 to "1"
end vector
vector End_Write_D1
set D1 to "k"
set Chip_Select_bar to "0"
set Write_bar to "1"
end vector
vector End_Write_D2
set D2 to "k"
set Chip_Select_bar to "0"
set Write_bar to "1"
end vector
vector End_Write_D3
set D3 to "k"
set Chip_Select_bar to "0"
set Write_bar to "1"
end vector
vector End_Write_D4
set D4 to "k"
set Chip_Select_bar to "0"
set Write_bar to "1"
end vector
!*****************************************************************************
!*****************************************************************************
sub Write_data (Address,Data)
execute Address
execute Data
execute End_Write
execute End_Cycle
end sub
sub Read_Data (Address,Data)
execute Address
execute Data
execute End_Cycle
end sub
!AT The following subroutines have been added for a minimum pins test.
!AT Vectors in the subroutine "Write_data" reference the entire data bus.
!AT Therefore this subroutine was copied and modified to reference only
!AT a single pin of the data bus. The subroutine "Read_data" did not
!AT require any modification as all references to the data bus are made
!AT via a passed parameter (Data). This reference can be modified in the
!AT call statement.
sub Write_data_Dx (Address, Data_Dx, End_Write_Dx)
execute Address
execute Data_Dx
execute End_Write_Dx
execute End_Cycle
end sub
!******************************************************************************
!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D1.
unit "awaretest D1 Test"
call Write_data_Dx (Address_0000, Data_in_D1_0, End_Write_D1)
call Read_data (Address_0000, Data_out_Q1_0)
call Write_data_Dx (Address_0000, Data_in_D1_1, End_Write_D1)
call Read_data (Address_0000, Data_out_Q1_1)
end unit
unit "awaretest D2 Test"
call Write_data_Dx (Address_0000, Data_in_D2_0, End_Write_D2)
call Read_data (Address_0000, Data_out_Q2_0)
call Write_data_Dx (Address_0000, Data_in_D2_1, End_Write_D2)
call Read_data (Address_0000, Data_out_Q2_1)
end unit
unit "awaretest D3 Test"
call Write_data_Dx (Address_0000, Data_in_D3_0, End_Write_D3)
call Read_data (Address_0000, Data_out_Q3_0)
call Write_data_Dx (Address_0000, Data_in_D3_1, End_Write_D3)
call Read_data (Address_0000, Data_out_Q3_1)
end unit
unit "awaretest D4 Test"
call Write_data_Dx (Address_0000, Data_in_D4_0, End_Write_D4)
call Read_data (Address_0000, Data_out_Q4_0)
call Write_data_Dx (Address_0000, Data_in_D4_1, End_Write_D4)
call Read_data (Address_0000, Data_out_Q4_1)
end unit
unit "RAM TEST"
! Initialize Ram cells
call Write_Data (Address_0000,Data_in_1111)
call Write_Data (Address_0001,Data_in_1111)
call Write_Data (Address_0011,Data_in_1111)
call Write_Data (Address_0111,Data_in_1111)
call Write_Data (Address_1111,Data_in_0000)
! Write to Ram cells with greycode patern
call Write_Data (Address_0000,Data_in_0000)
call Write_Data (Address_0001,Data_in_0001)
call Write_Data (Address_0011,Data_in_0011)
call Write_Data (Address_0111,Data_in_0111)
call Write_Data (Address_1111,Data_in_1111)
! Read Ram cells
call Read_data (Address_0000,Data_out_0000)
call Read_data (Address_0001,Data_out_0001)
call Read_data (Address_0011,Data_out_0011)
call Read_data (Address_0111,Data_out_0111)
call Read_data (Address_1111,Data_out_1111)
end unit
! End of test