!!!! 6 0 1 986833228 V1444 ! Device : 7484 ! Function : RAM open_collector static 16_bit ! revision : B.01.00 ! safeguard : hi_oc_ttl ! Modifications : Modified for AwareTest xi ! warning "This library has not been verified with hardware." sequential vector cycle 2u receive delay 1.9u assign VCC to pins 5 assign GND to pins 12 assign Address to pins 1,2,3,4,9,8,7,6 assign Write_1 to pins 16,15 assign Write_0 to pins 11,10 assign Sense_1 to pins 14 assign Sense_0 to pins 13 family TTL power VCC, GND inputs Address, Write_1, Write_0 outputs Sense_1, Sense_0 trace Sense_1,Sense_0 to Address,Write_1,Write_0 disable Sense_0 with Address to "00000000" disable Sense_1 with Address to "00000000" outputs limited to 1 at "0", 1 at "1" !*********************************************************************** !*********************************************************************** vector Write_0_to_Cell_1 set Write_0 to "11" set Write_1 to "00" set Address to "00011000" end vector vector Write_0_to_Cell_2 set Write_0 to "11" set Write_1 to "00" set Address to "00010100" end vector vector Write_0_to_Cell_3 set Write_0 to "11" set Write_1 to "00" set Address to "00010010" end vector vector Write_0_to_Cell_4 set Write_0 to "11" set Write_1 to "00" set Address to "00010001" end vector vector Write_0_to_Cell_5 set Write_0 to "11" set Write_1 to "00" set Address to "00101000" end vector vector Write_0_to_Cell_6 set Write_0 to "11" set Write_1 to "00" set Address to "01001000" end vector vector Write_0_to_Cell_7 set Write_0 to "11" set Write_1 to "00" set Address to "10001000" end vector vector Write_1_to_Cell_1 set Write_0 to "01" set Write_1 to "11" set Address to "00011000" end vector vector Write_1_to_Cell_2 set Write_0 to "01" set Write_1 to "11" set Address to "00010100" end vector vector Write_1_to_Cell_3 set Write_0 to "01" set Write_1 to "11" set Address to "00010010" end vector vector Write_1_to_Cell_4 set Write_0 to "01" set Write_1 to "11" set Address to "00010001" end vector vector Write_1_to_Cell_5 set Write_0 to "01" set Write_1 to "11" set Address to "00101000" end vector vector Write_1_to_Cell_6 set Write_0 to "01" set Write_1 to "11" set Address to "01001000" end vector vector Write_1_to_Cell_7 set Write_0 to "01" set Write_1 to "11" set Address to "10001000" end vector vector Address_00000000 set Write_0 to "00" set Write_1 to "00" set Address to "00000000" end vector vector Read_0_from_Cell_1 set Write_0 to "10" set Write_1 to "01" set Address to "00011000" set Sense_0 to "1" set Sense_1 to "0" end vector vector Read_0_from_Cell_2 set Write_0 to "10" set Write_1 to "01" set Address to "00010100" set Sense_0 to "1" set Sense_1 to "0" end vector vector Read_0_from_Cell_3 set Write_0 to "10" set Write_1 to "01" set Address to "00010010" set Sense_0 to "1" set Sense_1 to "0" end vector vector Read_0_from_Cell_4 set Write_0 to "10" set Write_1 to "01" set Address to "00010001" set Sense_0 to "1" set Sense_1 to "0" end vector vector Read_0_from_Cell_5 set Write_0 to "10" set Write_1 to "01" set Address to "00101000" set Sense_0 to "1" set Sense_1 to "0" end vector vector Read_0_from_Cell_6 set Write_0 to "10" set Write_1 to "01" set Address to "01001000" set Sense_0 to "1" set Sense_1 to "0" end vector vector Read_0_from_Cell_7 set Write_0 to "10" set Write_1 to "01" set Address to "10001000" set Sense_0 to "1" set Sense_1 to "0" end vector vector Read_1_from_Cell_1 set Write_0 to "01" set Write_1 to "10" set Address to "00011000" set Sense_0 to "0" set Sense_1 to "1" end vector vector Read_1_from_Cell_2 set Write_0 to "01" set Write_1 to "10" set Address to "00010100" set Sense_0 to "0" set Sense_1 to "1" end vector vector Read_1_from_Cell_3 set Write_0 to "01" set Write_1 to "10" set Address to "00010010" set Sense_0 to "0" set Sense_1 to "1" end vector vector Read_1_from_Cell_4 set Write_0 to "01" set Write_1 to "10" set Address to "00010001" set Sense_0 to "0" set Sense_1 to "1" end vector vector Read_1_from_Cell_5 set Write_0 to "01" set Write_1 to "10" set Address to "00101000" set Sense_0 to "0" set Sense_1 to "1" end vector vector Read_1_from_Cell_6 set Write_0 to "01" set Write_1 to "10" set Address to "01001000" set Sense_0 to "0" set Sense_1 to "1" end vector vector Read_1_from_Cell_7 set Write_0 to "01" set Write_1 to "10" set Address to "10001000" set Sense_0 to "0" set Sense_1 to "1" end vector !AT The following vectors have been added for a minimum pins test. Any !AT vectors that references the data bus was copied and modified to reference !AT only a single pin of the data bus. vector Read_S0_1_from_Cell_1 set Write_0 to "10" set Write_1 to "01" set Address to "00011000" set Sense_0 to "1" end vector vector Read_S0_0_from_Cell_1 set Write_0 to "01" set Write_1 to "10" set Address to "00011000" set Sense_0 to "0" end vector vector Read_S1_0_from_Cell_1 set Write_0 to "10" set Write_1 to "01" set Address to "00011000" set Sense_1 to "0" end vector vector Read_S1_1_from_Cell_1 set Write_0 to "01" set Write_1 to "10" set Address to "00011000" set Sense_1 to "1" end vector !*********************************************************************** !*********************************************************************** !AT The following AwareTest units have been added for minimum pins tests. Each !AT unit tests a separate data pin starting with S0. unit "awaretest S0 Test" execute Write_1_to_Cell_1 execute Address_00000000 execute Read_S0_1_from_Cell_1 execute Write_0_to_Cell_1 execute Address_00000000 execute Read_S0_0_from_Cell_1 end unit unit "awaretest S1 Test" execute Write_1_to_Cell_1 execute Address_00000000 execute Read_S1_0_from_Cell_1 execute Write_0_to_Cell_1 execute Address_00000000 execute Read_S1_1_from_Cell_1 end unit ! This test will detect pin faults. Seven cells are verified for writing ! and reading 1's and 0's. These cells are so chosen that each address ! input will be checked both in the high state and the low state. ! This test will not allow for any of the write lines to be tied high. ! In such a case, change the setting of group Write_0 or Write_1 as ! needed in all of the vectors. sub Load_Test_Cells_with_1 execute Write_1_to_Cell_1 execute Write_1_to_Cell_2 execute Write_1_to_Cell_3 execute Write_1_to_Cell_4 execute Write_1_to_Cell_5 execute Write_1_to_Cell_6 execute Write_1_to_Cell_7 end sub unit "RAM test, Cell 1" call Load_Test_Cells_with_1 execute Write_0_to_Cell_1 execute Address_00000000 execute Read_0_from_Cell_2 execute Read_0_from_Cell_3 execute Read_0_from_Cell_4 execute Read_0_from_Cell_5 execute Read_0_from_Cell_6 execute Read_0_from_Cell_7 execute Read_1_from_Cell_1 end unit unit "RAM test, Cell 2" call Load_Test_Cells_with_1 execute Write_0_to_Cell_2 execute Address_00000000 execute Read_0_from_Cell_1 execute Read_0_from_Cell_3 execute Read_0_from_Cell_4 execute Read_0_from_Cell_5 execute Read_0_from_Cell_6 execute Read_0_from_Cell_7 execute Read_1_from_Cell_2 end unit unit "RAM test, Cell 3" call Load_Test_Cells_with_1 execute Write_0_to_Cell_3 execute Address_00000000 execute Read_0_from_Cell_1 execute Read_0_from_Cell_2 execute Read_0_from_Cell_4 execute Read_0_from_Cell_5 execute Read_0_from_Cell_6 execute Read_0_from_Cell_7 execute Read_1_from_Cell_3 end unit unit "RAM test, Cell 4" call Load_Test_Cells_with_1 execute Write_0_to_Cell_4 execute Address_00000000 execute Read_0_from_Cell_1 execute Read_0_from_Cell_2 execute Read_0_from_Cell_3 execute Read_0_from_Cell_5 execute Read_0_from_Cell_6 execute Read_0_from_Cell_7 execute Read_1_from_Cell_4 end unit unit "RAM test, Cell 5" call Load_Test_Cells_with_1 execute Write_0_to_Cell_5 execute Address_00000000 execute Read_0_from_Cell_1 execute Read_0_from_Cell_2 execute Read_0_from_Cell_3 execute Read_0_from_Cell_4 execute Read_0_from_Cell_6 execute Read_0_from_Cell_7 execute Read_1_from_Cell_5 end unit unit "RAM test, Cell 6" call Load_Test_Cells_with_1 execute Write_0_to_Cell_6 execute Address_00000000 execute Read_0_from_Cell_1 execute Read_0_from_Cell_2 execute Read_0_from_Cell_3 execute Read_0_from_Cell_4 execute Read_0_from_Cell_5 execute Read_0_from_Cell_7 execute Read_1_from_Cell_6 end unit unit "RAM test, Cell 7" call Load_Test_Cells_with_1 execute Write_0_to_Cell_7 execute Address_00000000 execute Read_0_from_Cell_1 execute Read_0_from_Cell_2 execute Read_0_from_Cell_3 execute Read_0_from_Cell_4 execute Read_0_from_Cell_5 execute Read_0_from_Cell_6 execute Read_1_from_Cell_7 end unit ! End of Test