!!!! 6 0 1 987033607 V3a08 ! Device : 4099 ! Function : Latch totem 8_Bit ! revision : B.01.00 ! safeguard : standard_cmos ! Modifications : Modified for AwareTest xi ! warning "This library has not been verified with hardware." sequential vector cycle 1u receive delay 900n assign VDD to pins 16 assign VSS to pins 8 assign Data_Input to pins 3 assign Write_Disable to pins 4 assign Reset to pins 2 assign Address to pins 7,6,5 assign Data_Outputs to pins 1,15,14,13,12,11,10,9 assign Data_D0 to pins 9 !AT Added for minimum pin test. assign Data_D1 to pins 10 !AT Added for minimum pin test. assign Data_D2 to pins 11 !AT Added for minimum pin test. assign Data_D3 to pins 12 !AT Added for minimum pin test. assign Data_D4 to pins 13 !AT Added for minimum pin test. assign Data_D5 to pins 14 !AT Added for minimum pin test. assign Data_D6 to pins 15 !AT Added for minimum pin test. assign Data_D7 to pins 1 !AT Added for minimum pin test. power VDD, VSS family CMOS inputs Data_Input, Write_Disable, Reset, Address outputs Data_Outputs outputs Data_D0, Data_D1, Data_D2, Data_D3 !AT Added for minimum pin test. outputs Data_D4, Data_D5, Data_D6, Data_D7 !AT Added for minimum pin test. trace Data_Outputs to Data_Input, Write_Disable, Reset, Address !*********************************************************************** !*********************************************************************** vector Address_000 set Reset to "0" set Address to "000" end vector vector Address_001 set Reset to "0" set Address to "001" end vector vector Address_010 set Reset to "0" set Address to "010" end vector vector Address_011 set Reset to "0" set Address to "011" end vector vector Address_100 set Reset to "0" set Address to "100" end vector vector Address_101 set Reset to "0" set Address to "101" end vector vector Address_110 set Reset to "0" set Address to "110" end vector vector Address_111 set Reset to "0" set Address to "111" end vector vector Enable_Writing set Reset to "0" set Address to "KKK" set Write_Disable to "0" end vector vector Data_Input_0 set Reset to "K" set Address to "KKK" set Write_Disable to "K" set Data_Input to "0" end vector vector Data_Input_1 set Reset to "K" set Address to "KKK" set Write_Disable to "K" set Data_Input to "1" end vector vector Data_Output_XXXXXXX0 set Reset to "K" set Address to "KKK" set Write_Disable to "K" set Data_Input to "K" set Data_Outputs to "XXXXXXX0" end vector vector Data_Output_XXXXXXX1 set Reset to "K" set Address to "KKK" set Write_Disable to "K" set Data_Input to "K" set Data_Outputs to "XXXXXXX1" end vector vector Data_Output_XXXXXX0X set Reset to "K" set Address to "KKK" set Write_Disable to "K" set Data_Input to "K" set Data_Outputs to "XXXXXX0X" end vector vector Data_Output_XXXXXX1X set Reset to "K" set Address to "KKK" set Write_Disable to "K" set Data_Input to "K" set Data_Outputs to "XXXXXX1X" end vector vector Data_Output_XXXXX0XX set Reset to "K" set Address to "KKK" set Write_Disable to "K" set Data_Input to "K" set Data_Outputs to "XXXXX0XX" end vector vector Data_Output_XXXXX1XX set Reset to "K" set Address to "KKK" set Write_Disable to "K" set Data_Input to "K" set Data_Outputs to "XXXXX1XX" end vector vector Data_Output_XXXX0XXX set Reset to "K" set Address to "KKK" set Write_Disable to "K" set Data_Input to "K" set Data_Outputs to "XXXX0XXX" end vector vector Data_Output_XXXX1XXX set Reset to "K" set Address to "KKK" set Write_Disable to "K" set Data_Input to "K" set Data_Outputs to "XXXX1XXX" end vector vector Data_Output_XXX0XXXX set Reset to "K" set Address to "KKK" set Write_Disable to "K" set Data_Input to "K" set Data_Outputs to "XXX0XXXX" end vector vector Data_Output_XXX1XXXX set Reset to "K" set Address to "KKK" set Write_Disable to "K" set Data_Input to "K" set Data_Outputs to "XXX1XXXX" end vector vector Data_Output_XX0XXXXX set Reset to "K" set Address to "KKK" set Write_Disable to "K" set Data_Input to "K" set Data_Outputs to "XX0XXXXX" end vector vector Data_Output_XX1XXXXX set Reset to "K" set Address to "KKK" set Write_Disable to "K" set Data_Input to "K" set Data_Outputs to "XX1XXXXX" end vector vector Data_Output_X0XXXXXX set Reset to "K" set Address to "KKK" set Write_Disable to "K" set Data_Input to "K" set Data_Outputs to "X0XXXXXX" end vector vector Data_Output_X1XXXXXX set Reset to "K" set Address to "KKK" set Write_Disable to "K" set Data_Input to "K" set Data_Outputs to "X1XXXXXX" end vector vector Data_Output_0XXXXXXX set Reset to "K" set Address to "KKK" set Write_Disable to "K" set Data_Input to "K" set Data_Outputs to "0XXXXXXX" end vector vector Data_Output_1XXXXXXX set Reset to "K" set Address to "KKK" set Write_Disable to "K" set Data_Input to "K" set Data_Outputs to "1XXXXXXX" end vector vector Latch_Data set Address to "KKK" set Data_Input to "K" set Reset to "K" set Write_Disable to "1" end vector vector Reset_Device set Reset to "1" set Write_Disable to "1" set Data_Outputs to "00000000" end vector !AT The following vectors have been added for a minimum pins test. Any !AT vectors that references the data bus was copied and modified to reference !AT only a single pin of the data bus. vector Data_Output_D0_0 set Reset to "K" set Address to "KKK" set Write_Disable to "K" set Data_Input to "K" set Data_D0 to "0" end vector vector Data_Output_D0_1 set Reset to "K" set Address to "KKK" set Write_Disable to "K" set Data_Input to "K" set Data_D0 to "1" end vector vector Data_Output_D1_0 set Reset to "K" set Address to "KKK" set Write_Disable to "K" set Data_Input to "K" set Data_D1 to "0" end vector vector Data_Output_D1_1 set Reset to "K" set Address to "KKK" set Write_Disable to "K" set Data_Input to "K" set Data_D1 to "1" end vector vector Data_Output_D2_0 set Reset to "K" set Address to "KKK" set Write_Disable to "K" set Data_Input to "K" set Data_D2 to "0" end vector vector Data_Output_D2_1 set Reset to "K" set Address to "KKK" set Write_Disable to "K" set Data_Input to "K" set Data_D2 to "1" end vector vector Data_Output_D3_0 set Reset to "K" set Address to "KKK" set Write_Disable to "K" set Data_Input to "K" set Data_D3 to "0" end vector vector Data_Output_D3_1 set Reset to "K" set Address to "KKK" set Write_Disable to "K" set Data_Input to "K" set Data_D3 to "1" end vector vector Data_Output_D4_0 set Reset to "K" set Address to "KKK" set Write_Disable to "K" set Data_Input to "K" set Data_D4 to "0" end vector vector Data_Output_D4_1 set Reset to "K" set Address to "KKK" set Write_Disable to "K" set Data_Input to "K" set Data_D4 to "1" end vector vector Data_Output_D5_0 set Reset to "K" set Address to "KKK" set Write_Disable to "K" set Data_Input to "K" set Data_D5 to "0" end vector vector Data_Output_D5_1 set Reset to "K" set Address to "KKK" set Write_Disable to "K" set Data_Input to "K" set Data_D5 to "1" end vector vector Data_Output_D6_0 set Reset to "K" set Address to "KKK" set Write_Disable to "K" set Data_Input to "K" set Data_D6 to "0" end vector vector Data_Output_D6_1 set Reset to "K" set Address to "KKK" set Write_Disable to "K" set Data_Input to "K" set Data_D6 to "1" end vector vector Data_Output_D7_0 set Reset to "K" set Address to "KKK" set Write_Disable to "K" set Data_Input to "K" set Data_D7 to "0" end vector vector Data_Output_D7_1 set Reset to "K" set Address to "KKK" set Write_Disable to "K" set Data_Input to "K" set Data_D7 to "1" end vector vector Reset_Device_Dx set Reset to "1" set Write_Disable to "1" end vector !*********************************************************************** !*********************************************************************** !AT The following AwareTest units have been added for minimum pins tests. Each !AT unit tests a separate data pin starting with D0. unit "awaretest D0 Test" execute Address_000 execute Enable_Writing execute Data_Input_0 execute Data_Output_D0_0 execute Data_Input_1 execute Data_Output_D0_1 execute Reset_Device_Dx end unit unit "awaretest D1 Test" execute Address_001 execute Enable_Writing execute Data_Input_0 execute Data_Output_D1_0 execute Data_Input_1 execute Data_Output_D1_1 execute Reset_Device_Dx end unit unit "awaretest D2 Test" execute Address_010 execute Enable_Writing execute Data_Input_0 execute Data_Output_D2_0 execute Data_Input_1 execute Data_Output_D2_1 execute Reset_Device_Dx end unit unit "awaretest D3 Test" execute Address_011 execute Enable_Writing execute Data_Input_0 execute Data_Output_D3_0 execute Data_Input_1 execute Data_Output_D3_1 execute Reset_Device_Dx end unit unit "awaretest D4 Test" execute Address_100 execute Enable_Writing execute Data_Input_0 execute Data_Output_D4_0 execute Data_Input_1 execute Data_Output_D4_1 execute Reset_Device_Dx end unit unit "awaretest D5 Test" execute Address_101 execute Enable_Writing execute Data_Input_0 execute Data_Output_D5_0 execute Data_Input_1 execute Data_Output_D5_1 execute Reset_Device_Dx end unit unit "awaretest D6 Test" execute Address_110 execute Enable_Writing execute Data_Input_0 execute Data_Output_D6_0 execute Data_Input_1 execute Data_Output_D6_1 execute Reset_Device_Dx end unit unit "awaretest D7 Test" execute Address_111 execute Enable_Writing execute Data_Input_0 execute Data_Output_D7_0 execute Data_Input_1 execute Data_Output_D7_1 execute Reset_Device_Dx end unit unit "Latch 0 test" execute Address_000 execute Enable_Writing execute Data_Input_0 execute Data_Output_XXXXXXX0 execute Data_Input_1 execute Data_Output_XXXXXXX1 execute Latch_Data execute Data_Input_0 execute Data_Output_XXXXXXX1 execute Reset_Device end unit unit "Latch 1 test" execute Address_001 execute Enable_Writing execute Data_Input_0 execute Data_Output_XXXXXX0X execute Data_Input_1 execute Data_Output_XXXXXX1X execute Latch_Data execute Data_Input_0 execute Data_Output_XXXXXX1X execute Reset_Device end unit unit "Latch 2 test" execute Address_010 execute Enable_Writing execute Data_Input_0 execute Data_Output_XXXXX0XX execute Data_Input_1 execute Data_Output_XXXXX1XX execute Latch_Data execute Data_Input_0 execute Data_Output_XXXXX1XX execute Reset_Device end unit unit "Latch 3 test" execute Address_011 execute Enable_Writing execute Data_Input_0 execute Data_Output_XXXX0XXX execute Data_Input_1 execute Data_Output_XXXX1XXX execute Latch_Data execute Data_Input_0 execute Data_Output_XXXX1XXX execute Reset_Device end unit unit "Latch 4 test" execute Address_100 execute Enable_Writing execute Data_Input_0 execute Data_Output_XXX0XXXX execute Data_Input_1 execute Data_Output_XXX1XXXX execute Latch_Data execute Data_Input_0 execute Data_Output_XXX1XXXX execute Reset_Device end unit unit "Latch 5 test" execute Address_101 execute Enable_Writing execute Data_Input_0 execute Data_Output_XX0XXXXX execute Data_Input_1 execute Data_Output_XX1XXXXX execute Latch_Data execute Data_Input_0 execute Data_Output_XX1XXXXX execute Reset_Device end unit unit "Latch 6 test" execute Address_110 execute Enable_Writing execute Data_Input_0 execute Data_Output_X0XXXXXX execute Data_Input_1 execute Data_Output_X1XXXXXX execute Latch_Data execute Data_Input_0 execute Data_Output_X1XXXXXX execute Reset_Device end unit unit "Latch 7 test" execute Address_111 execute Enable_Writing execute Data_Input_0 execute Data_Output_0XXXXXXX execute Data_Input_1 execute Data_Output_1XXXXXXX execute Latch_Data execute Data_Input_0 execute Data_Output_1XXXXXXX execute Reset_Device end unit ! End of test