!!!!    6    0    1  987103770  V6cd8                                         

! Device           : 29705
! Function         : 16 X 4 Ait 2-Port Ram
! revision         : B.01.00
! safeguard        : hi_oc_als
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

sequential

vector cycle  500n
receive delay 400n

assign VCC    to pins 28
assign GND    to pins 14

assign Data_input         to pins    26,27,1,2
assign D3                 to pins    26
assign D2                 to pins    27
assign D1                 to pins    1
assign D0                 to pins    2

assign A_inputs           to pins    21,22,23,24
assign B_inputs           to pins    7,6,5,4
assign WE_bar_1           to pins    3
assign WE_bar_2           to pins    25
assign OE_A_bar           to pins    20
assign OE_B_bar           to pins    19
assign Latch_Enable       to pins    9
assign A_LO_bar           to pins    8

assign A_output           to pins    18,16,13,11
assign A3                 to pins    18
assign A2                 to pins    16
assign A1                 to pins    13
assign A0                 to pins    11

assign B_output           to pins    17,15,12,10
assign B3                 to pins    17
assign B2                 to pins    15
assign B1                 to pins    12
assign B0                 to pins    10

family TTL

power  VCC,GND

inputs   Data_input, A_inputs, B_inputs, WE_bar_1, WE_bar_2
inputs   OE_A_bar, OE_B_bar, Latch_Enable, A_LO_bar
inputs   D0, D1, D2, D3              !AT Added for minimum pin test.

outputs  A_output, B_output
outputs  A0, A1, A2, A3              !AT Added for minimum pin test.
outputs  B0, B1, B2, B3              !AT Added for minimum pin test.


disable  A_output with OE_A_bar to "1"
disable  B_output with OE_B_bar to "1"

when OE_A_bar is "1" inactive A_output
when OE_B_bar is "1" inactive B_output

trace A3 to D3, WE_bar_1, WE_bar_2, OE_A_bar, Latch_Enable, A_LO_bar
trace A2 to D2, WE_bar_1, WE_bar_2, OE_A_bar, Latch_Enable, A_LO_bar
trace A1 to D1, WE_bar_1, WE_bar_2, OE_A_bar, Latch_Enable, A_LO_bar
trace A0 to D0, WE_bar_1, WE_bar_2, OE_A_bar, Latch_Enable, A_LO_bar

trace A3 to A_inputs, B_inputs
trace A2 to A_inputs, B_inputs
trace A1 to A_inputs, B_inputs
trace A0 to A_inputs, B_inputs

trace B3 to D3, WE_bar_1, WE_bar_2, OE_B_bar, Latch_Enable, B_inputs
trace B2 to D2, WE_bar_1, WE_bar_2, OE_B_bar, Latch_Enable, B_inputs
trace B1 to D1, WE_bar_1, WE_bar_2, OE_B_bar, Latch_Enable, B_inputs
trace B0 to D0, WE_bar_1, WE_bar_2, OE_B_bar, Latch_Enable, B_inputs

!**************************************************************************
!**************************************************************************

vector    Setup
     set  A_LO_bar             to  "1"
     set  OE_A_bar             to  "0"
     set  OE_B_bar             to  "0"
     set  WE_bar_1             to  "0"
     set  WE_bar_2             to  "0"
     set  Latch_Enable         to  "0"
     set  A_inputs             to  "0000"
     set  B_inputs             to  "0000"
     set  Data_input           to  "0000"
end vector

vector    Keep_inputs
     set  A_LO_bar             to  "k"
     set  OE_A_bar             to  "k"
     set  OE_B_bar             to  "k"
     set  WE_bar_1             to  "k"
     set  WE_bar_2             to  "k"
     set  Latch_Enable         to  "k"
     set  A_inputs             to  "kkkk"
     set  B_inputs             to  "kkkk"
     set  Data_input           to  "kkkk"
end vector

warning "If one of the write enable lines is tied low then user must"
warning "comment out that set command."

vector    Write_enable_false
     initialize to Keep_inputs
     set  WE_bar_1    to "1"          !if WE_1 free use this line
     set  WE_bar_2    to "1"          !else use this line
end vector

vector    Write_enable_1_false
     initialize to Keep_inputs
     set  WE_bar_1    to "1"
end vector

vector    Write_enable_2_false
     initialize to Keep_inputs
     set  WE_bar_2    to "1"
end vector

vector    Write_enable_true
     initialize to Keep_inputs
     set  WE_bar_1    to "0"
     set  WE_bar_2    to "0"
end vector

vector    Count_address_A
     initialize to Keep_inputs
     set  A_inputs    to "0000"
     upcounter  A_inputs
end vector

vector    Count_address_B
     initialize to Write_enable_false
     set  B_inputs    to "0000"
     upcounter  B_inputs
end vector


vector    Count_data_input
     initialize to Keep_inputs
     set  Data_input  to "0000"
     upcounter  Data_input
end vector

vector    Count_A_out
     initialize to Keep_inputs
     set  A_output    to "0000"
     upcounter A_output
end vector

vector    Count_B_out
     initialize to Keep_inputs
     set  B_output    to "0000"
     upcounter B_output
end vector


vector    A_output_enable
     initialize to Keep_inputs
     set  OE_A_bar    to "0"
     set  OE_B_bar    to "1"
     set  Latch_enable to"1"
end vector

vector    A_output_enable_false
     initialize to Keep_inputs
     set  OE_A_bar    to "1"
     set  OE_B_bar    to "1"
     set  Latch_enable to"1"
end vector

vector    B_output_enable
     initialize to Keep_inputs
     set  OE_A_bar    to "1"
     set  OE_B_bar    to "0"
     set  Latch_enable to"1"
end vector

vector    B_output_enable_false
     initialize to Keep_inputs
     set  OE_A_bar    to "1"
     set  OE_B_bar    to "1"
     set  Latch_enable to"1"
end vector


vector    Force_A_low
     initialize to Keep_inputs
     set  A_LO_bar    to "0"
     set  A_output    to "0000"
 end vector

vector    Force_A_high
     initialize to Keep_inputs
     set  A_LO_bar    to "1"
     set  A_output    to "1111"
 end vector


vector    B_inputs_1010
     initialize to Write_enable_false
     set  B_inputs    to "1010"
end vector

vector    Data_input_1111
     initialize to Keep_inputs
     set  Data_input  to "1111"
end vector

vector    Data_input_0000
     initialize to Keep_inputs
     set  Data_input  to "0000"
end vector

vector    A_inputs_0000
     initialize to Keep_inputs
     set  A_inputs    to "0000"
end vector

vector    A_inputs_1111
     initialize to Keep_inputs
     set  A_inputs    to "1111"
end vector

vector    B_inputs_0000
     initialize to Keep_inputs
     set  B_inputs    to "0000"
end vector

vector    B_inputs_1111
     initialize to Keep_inputs
     set  B_inputs    to "1111"
end vector

vector    A_output_0000
     initialize to Keep_inputs
     set  A_output    to "0000"
end vector

vector    A_output_1111
     initialize to Keep_inputs
     set  A_output    to "1111"
end vector

vector    B_output_0000
     initialize to Keep_inputs
     set  B_output    to "0000"
end vector

vector    B_output_1111
     initialize to Keep_inputs
     set  B_output    to "1111"
end vector

vector    Latch_enable_low
     initialize to Keep_inputs
     set  Latch_Enable to "0"
end vector

vector    Latch_enable_high
     initialize to Keep_inputs
     set  Latch_Enable to "1"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector    Setup_D0
     set  A_LO_bar             to  "1"
     set  OE_A_bar             to  "0"
     set  OE_B_bar             to  "0"
     set  WE_bar_1             to  "0"
     set  WE_bar_2             to  "0"
     set  Latch_Enable         to  "0"
     set  A_inputs             to  "0000"
     set  B_inputs             to  "0000"
     set  D0                   to  "0"
end vector

vector    Keep_inputs_D0
     set  A_LO_bar             to  "k"
     set  OE_A_bar             to  "k"
     set  OE_B_bar             to  "k"
     set  WE_bar_1             to  "k"
     set  WE_bar_2             to  "k"
     set  Latch_Enable         to  "k"
     set  A_inputs             to  "kkkk"
     set  B_inputs             to  "kkkk"
     set  D0                   to  "k"
end vector

vector    A_inputs_0000_D0
     initialize to Keep_inputs_D0
     set  A_inputs    to "0000"
end vector

vector    B_inputs_0000_D0
     initialize to Keep_inputs_D0
     set  B_inputs    to "0000"
end vector

vector    Data_input_D0_0
     initialize to Keep_inputs_D0
     set  D0          to "0"
end vector

vector    Data_input_D0_1
     initialize to Keep_inputs_D0
     set  D0          to "1"
end vector

vector    Write_enable_true_D0
     initialize to Keep_inputs_D0
     set  WE_bar_1    to "0"
     set  WE_bar_2    to "0"
end vector

vector    Write_enable_false_D0
     initialize to Keep_inputs_D0
     set  WE_bar_1    to "1"
     set  WE_bar_2    to "1"
end vector

vector    A_output_enable_A0
     initialize to Keep_inputs_D0
     set  OE_A_bar    to "0"
     set  OE_B_bar    to "1"
     set  Latch_enable to"1"
end vector

vector    B_output_enable_B0
     initialize to Keep_inputs_D0
     set  OE_A_bar    to "1"
     set  OE_B_bar    to "0"
     set  Latch_enable to"1"
end vector

vector    A_output_A0_0
     initialize to Keep_inputs_D0
     set  A0          to "0"
end vector

vector    A_output_A0_1
     initialize to Keep_inputs_D0
     set  A0          to "1"
end vector

vector    B_output_B0_0
     initialize to Keep_inputs_D0
     set  B0          to "0"
end vector

vector    B_output_B0_1
     initialize to Keep_inputs_D0
     set  B0          to "1"
end vector

vector    Setup_D1
     set  A_LO_bar             to  "1"
     set  OE_A_bar             to  "0"
     set  OE_B_bar             to  "0"
     set  WE_bar_1             to  "0"
     set  WE_bar_2             to  "0"
     set  Latch_Enable         to  "0"
     set  A_inputs             to  "0000"
     set  B_inputs             to  "0000"
     set  D1                   to  "0"
end vector

vector    Keep_inputs_D1
     set  A_LO_bar             to  "k"
     set  OE_A_bar             to  "k"
     set  OE_B_bar             to  "k"
     set  WE_bar_1             to  "k"
     set  WE_bar_2             to  "k"
     set  Latch_Enable         to  "k"
     set  A_inputs             to  "kkkk"
     set  B_inputs             to  "kkkk"
     set  D1                   to  "k"
end vector

vector    A_inputs_0000_D1
     initialize to Keep_inputs_D1
     set  A_inputs    to "0000"
end vector

vector    B_inputs_0000_D1
     initialize to Keep_inputs_D1
     set  B_inputs    to "0000"
end vector

vector    Data_input_D1_0
     initialize to Keep_inputs_D1
     set  D1          to "0"
end vector

vector    Data_input_D1_1
     initialize to Keep_inputs_D1
     set  D1          to "1"
end vector

vector    Write_enable_true_D1
     initialize to Keep_inputs_D1
     set  WE_bar_1    to "0"
     set  WE_bar_2    to "0"
end vector

vector    Write_enable_false_D1
     initialize to Keep_inputs_D1
     set  WE_bar_1    to "1"
     set  WE_bar_2    to "1"
end vector

vector    A_output_enable_A1
     initialize to Keep_inputs_D1
     set  OE_A_bar    to "0"
     set  OE_B_bar    to "1"
     set  Latch_enable to"1"
end vector

vector    B_output_enable_B1
     initialize to Keep_inputs_D1
     set  OE_A_bar    to "1"
     set  OE_B_bar    to "0"
     set  Latch_enable to"1"
end vector

vector    A_output_A1_0
     initialize to Keep_inputs_D1
     set  A1          to "0"
end vector

vector    A_output_A1_1
     initialize to Keep_inputs_D1
     set  A1          to "1"
end vector

vector    B_output_B1_0
     initialize to Keep_inputs_D1
     set  B1          to "0"
end vector

vector    B_output_B1_1
     initialize to Keep_inputs_D1
     set  B1          to "1"
end vector

vector    Setup_D2
     set  A_LO_bar             to  "1"
     set  OE_A_bar             to  "0"
     set  OE_B_bar             to  "0"
     set  WE_bar_1             to  "0"
     set  WE_bar_2             to  "0"
     set  Latch_Enable         to  "0"
     set  A_inputs             to  "0000"
     set  B_inputs             to  "0000"
     set  D2                   to  "0"
end vector

vector    Keep_inputs_D2
     set  A_LO_bar             to  "k"
     set  OE_A_bar             to  "k"
     set  OE_B_bar             to  "k"
     set  WE_bar_1             to  "k"
     set  WE_bar_2             to  "k"
     set  Latch_Enable         to  "k"
     set  A_inputs             to  "kkkk"
     set  B_inputs             to  "kkkk"
     set  D2                   to  "k"
end vector

vector    A_inputs_0000_D2
     initialize to Keep_inputs_D2
     set  A_inputs    to "0000"
end vector

vector    B_inputs_0000_D2
     initialize to Keep_inputs_D2
     set  B_inputs    to "0000"
end vector

vector    Data_input_D2_0
     initialize to Keep_inputs_D2
     set  D2          to "0"
end vector

vector    Data_input_D2_1
     initialize to Keep_inputs_D2
     set  D2          to "1"
end vector

vector    Write_enable_true_D2
     initialize to Keep_inputs_D2
     set  WE_bar_1    to "0"
     set  WE_bar_2    to "0"
end vector

vector    Write_enable_false_D2
     initialize to Keep_inputs_D2
     set  WE_bar_1    to "1"
     set  WE_bar_2    to "1"
end vector

vector    A_output_enable_A2
     initialize to Keep_inputs_D2
     set  OE_A_bar    to "0"
     set  OE_B_bar    to "1"
     set  Latch_enable to"1"
end vector

vector    B_output_enable_B2
     initialize to Keep_inputs_D2
     set  OE_A_bar    to "1"
     set  OE_B_bar    to "0"
     set  Latch_enable to"1"
end vector

vector    A_output_A2_0
     initialize to Keep_inputs_D2
     set  A2          to "0"
end vector

vector    A_output_A2_1
     initialize to Keep_inputs_D2
     set  A2          to "1"
end vector

vector    B_output_B2_0
     initialize to Keep_inputs_D2
     set  B2          to "0"
end vector

vector    B_output_B2_1
     initialize to Keep_inputs_D2
     set  B2          to "1"
end vector

vector    Setup_D3
     set  A_LO_bar             to  "1"
     set  OE_A_bar             to  "0"
     set  OE_B_bar             to  "0"
     set  WE_bar_1             to  "0"
     set  WE_bar_2             to  "0"
     set  Latch_Enable         to  "0"
     set  A_inputs             to  "0000"
     set  B_inputs             to  "0000"
     set  D3                   to  "0"
end vector

vector    Keep_inputs_D3
     set  A_LO_bar             to  "k"
     set  OE_A_bar             to  "k"
     set  OE_B_bar             to  "k"
     set  WE_bar_1             to  "k"
     set  WE_bar_2             to  "k"
     set  Latch_Enable         to  "k"
     set  A_inputs             to  "kkkk"
     set  B_inputs             to  "kkkk"
     set  D3                   to  "k"
end vector

vector    A_inputs_0000_D3
     initialize to Keep_inputs_D3
     set  A_inputs    to "0000"
end vector

vector    B_inputs_0000_D3
     initialize to Keep_inputs_D3
     set  B_inputs    to "0000"
end vector

vector    Data_input_D3_0
     initialize to Keep_inputs_D3
     set  D3          to "0"
end vector

vector    Data_input_D3_1
     initialize to Keep_inputs_D3
     set  D3          to "1"
end vector

vector    Write_enable_true_D3
     initialize to Keep_inputs_D3
     set  WE_bar_1    to "0"
     set  WE_bar_2    to "0"
end vector

vector    Write_enable_false_D3
     initialize to Keep_inputs_D3
     set  WE_bar_1    to "1"
     set  WE_bar_2    to "1"
end vector

vector    A_output_enable_A3
     initialize to Keep_inputs_D3
     set  OE_A_bar    to "0"
     set  OE_B_bar    to "1"
     set  Latch_enable to"1"
end vector

vector    B_output_enable_B3
     initialize to Keep_inputs_D3
     set  OE_A_bar    to "1"
     set  OE_B_bar    to "0"
     set  Latch_enable to"1"
end vector

vector    A_output_A3_0
     initialize to Keep_inputs_D3
     set  A3          to "0"
end vector

vector    A_output_A3_1
     initialize to Keep_inputs_D3
     set  A3          to "1"
end vector

vector    B_output_B3_0
     initialize to Keep_inputs_D3
     set  B3          to "0"
end vector

vector    B_output_B3_1
     initialize to Keep_inputs_D3
     set  B3          to "1"
end vector

!***********************************************************************
!***********************************************************************

sub  Load_Ram
    execute  Setup                      !Load RAM with data
    preset counter Count_address_B
    preset counter Count_data_input
    repeat 16 times
       execute  Write_Enable_true
       count    Count_address_B
       count    Count_data_input
    end repeat
end sub

!***********************************************************************
!***********************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with A0.

unit   "awaretest A0 Test"

    execute  Setup_D0
    execute  B_inputs_0000_D0
    execute  Data_input_D0_0
    execute  Write_Enable_true_D0
    execute  Write_enable_false_D0
    execute  A_output_enable_A0
    execute  A_output_A0_0

    execute  B_inputs_0000_D0
    execute  Data_input_D0_1
    execute  Write_Enable_true_D0
    execute  Write_enable_false_D0
    execute  A_output_enable_A0
    execute  A_output_A0_1

end unit

unit   "awaretest A1 Test"

    execute  Setup_D1
    execute  B_inputs_0000_D1
    execute  Data_input_D1_0
    execute  Write_Enable_true_D1
    execute  Write_enable_false_D1
    execute  A_output_enable_A1
    execute  A_output_A1_0

    execute  B_inputs_0000_D1
    execute  Data_input_D1_1
    execute  Write_Enable_true_D1
    execute  Write_enable_false_D1
    execute  A_output_enable_A1
    execute  A_output_A1_1

end unit

unit   "awaretest A2 Test"

    execute  Setup_D2
    execute  B_inputs_0000_D2
    execute  Data_input_D2_0
    execute  Write_Enable_true_D2
    execute  Write_enable_false_D2
    execute  A_output_enable_A2
    execute  A_output_A2_0

    execute  B_inputs_0000_D2
    execute  Data_input_D2_1
    execute  Write_Enable_true_D2
    execute  Write_enable_false_D2
    execute  A_output_enable_A2
    execute  A_output_A2_1

end unit

unit   "awaretest A3 Test"

    execute  Setup_D3
    execute  B_inputs_0000_D3
    execute  Data_input_D3_0
    execute  Write_Enable_true_D3
    execute  Write_enable_false_D3
    execute  A_output_enable_A3
    execute  A_output_A3_0

    execute  B_inputs_0000_D3
    execute  Data_input_D3_1
    execute  Write_Enable_true_D3
    execute  Write_enable_false_D3
    execute  A_output_enable_A3
    execute  A_output_A3_1

end unit

unit   "awaretest B0 Test"

    execute  Setup_D0
    execute  B_inputs_0000_D0
    execute  Data_input_D0_0
    execute  Write_Enable_true_D0
    execute  Write_enable_false_D0
    execute  B_output_enable_B0
    execute  B_output_B0_0

    execute  B_inputs_0000_D0
    execute  Data_input_D0_1
    execute  Write_Enable_true_D0
    execute  Write_enable_false_D0
    execute  B_output_enable_B0
    execute  B_output_B0_1

end unit

unit   "awaretest B1 Test"

    execute  Setup_D1
    execute  B_inputs_0000_D1
    execute  Data_input_D1_0
    execute  Write_Enable_true_D1
    execute  Write_enable_false_D1
    execute  B_output_enable_B1
    execute  B_output_B1_0

    execute  B_inputs_0000_D1
    execute  Data_input_D1_1
    execute  Write_Enable_true_D1
    execute  Write_enable_false_D1
    execute  B_output_enable_B1
    execute  B_output_B1_1

end unit

unit   "awaretest B2 Test"

    execute  Setup_D2
    execute  B_inputs_0000_D2
    execute  Data_input_D2_0
    execute  Write_Enable_true_D2
    execute  Write_enable_false_D2
    execute  B_output_enable_B2
    execute  B_output_B2_0

    execute  B_inputs_0000_D2
    execute  Data_input_D2_1
    execute  Write_Enable_true_D2
    execute  Write_enable_false_D2
    execute  B_output_enable_B2
    execute  B_output_B2_1

end unit

unit   "awaretest B3 Test"

    execute  Setup_D3
    execute  B_inputs_0000_D3
    execute  Data_input_D3_0
    execute  Write_Enable_true_D3
    execute  Write_enable_false_D3
    execute  B_output_enable_B3
    execute  B_output_B3_0

    execute  B_inputs_0000_D3
    execute  Data_input_D3_1
    execute  Write_Enable_true_D3
    execute  Write_enable_false_D3
    execute  B_output_enable_B3
    execute  B_output_B3_1

end unit

unit  "Test Ram"                       !Read data from port A output
    call Load_Ram
    execute  A_output_enable
    preset counter Count_address_A
    preset counter Count_A_out
    repeat 16 times
       count    Count_address_A
       count    Count_A_out
    end repeat
                                       !Read data from port B output
    execute  B_output_enable
    preset counter Count_address_B
    preset counter Count_B_out
    repeat 16 times
       count    Count_address_B
       count    Count_B_out
    end repeat
end unit

unit  "Write Enable 1 Test"            !Write enable 1 input pin test
    execute  Setup
    execute  B_inputs_1010
    execute  Data_input_1111
    execute  Write_Enable_true
    execute  Write_Enable_1_false
    execute  Data_input_0000
    execute  B_output_enable
    execute  B_output_1111
end unit

unit  "Write Enable 2 Test"            !Write enable 2 input pin test
    execute  Setup
    execute  B_inputs_1010
    execute  Data_input_1111
    execute  Write_Enable_true
    execute  Write_Enable_2_false
    execute  Data_input_0000
    execute  B_output_enable
    execute  B_output_1111
end unit

unit  "Output Enable A"
    call  Load_Ram
    execute  A_output_enable
    execute  A_inputs_0000
    execute  A_output_0000
    execute  A_output_enable_false
    execute  A_output_1111

    execute  B_output_enable
    execute  B_inputs_0000
    execute  B_output_0000
    execute  B_output_enable_false
    execute  B_output_1111
end unit

unit  "Force Output A Zero"            !Set output port A to all Zeros
    execute  Setup
    execute  A_output_enable
    execute  B_inputs_0000
    execute  Data_input_1111
    execute  Write_enable_true
    execute  A_inputs_0000
    execute  Force_A_low
    execute  Force_A_high
end unit

unit  "Latch Enable Test"
    execute  Setup
    call Load_Ram
    execute  A_output_enable
    execute  A_inputs_0000
    execute  A_output_0000
    execute  Latch_enable_low
    execute  A_inputs_1111
    execute  A_output_0000

    execute  B_output_enable
    execute  B_inputs_0000
    execute  B_output_0000
    execute  Latch_enable_low
    execute  B_inputs_1111
    execute  B_output_0000

end unit