!!!! 6 0 1 986840400 V1e62
! Device : 2142
! Function : Static RAM 3-state 1k x 4
! revision : B.01.00
! safeguard : med_out_mos
! Modifications : Modified for AwareTest xi
!
warning "This library has not been verified with hardware."
sequential
warning "Pull-ups are required to test high-impedance outputs."
vector cycle 1000n
receive delay 900n
assign VCC to pins 20
assign GND to pins 10
assign Address to pins 17,18,19,1,2,3,4,8,7,6
assign Data to pins 12,13,14,15
assign Data_D0 to pins 15 !AT Added for minimum pin test.
assign Data_D1 to pins 14 !AT Added for minimum pin test.
assign Data_D2 to pins 13 !AT Added for minimum pin test.
assign Data_D3 to pins 12 !AT Added for minimum pin test.
assign Chip_select_1_bar to pins 9
assign Chip_select_2 to pins 5
assign Chip_selects to pins 9,5
assign Write_enable_bar to pins 11
assign Output_disable to pins 16
family TTL
power VCC, GND
inputs Address, Write_enable_bar, Output_disable
inputs Chip_select_1_bar, Chip_select_2, Chip_selects
bidirectional Data
bidirectional Data_D0, Data_D1, Data_D2, Data_D3 !AT Added for min. pin test.
when Write_enable_bar is "0" inputs Data
when Write_enable_bar is "1" outputs Data
when Chip_select_1_bar is "1" inactive Data
when Chip_select_2 is "0" inactive Data
when Output_disable is "1" inactive Data
trace Data to Address, Write_enable_bar, Output_disable
trace Data to Chip_select_1_bar, Chip_select_2, Chip_selects
disable Data with Chip_select_1_bar to "1"
disable Data with Chip_select_2 to "0"
disable Data with Output_disable to "1"
!***************************************************************
!***************************************************************
vector Disable
set Write_enable_bar to "1"
set Chip_selects to "10"
set Output_disable to "1"
end vector
vector Write_enable
set Address to "kkkkkkkkkk"
set Write_enable_bar to "0"
set Chip_selects to "01"
set Output_disable to "k"
end vector
vector Write_enable_false
drive Data
set Address to "kkkkkkkkkk"
set Data to "kkkk"
set Write_enable_bar to "1"
set Chip_selects to "10"
set Output_disable to "k"
end vector
vector Chip_select_1_false
drive Data
set Address to "kkkkkkkkkk"
set Write_enable_bar to "k"
set Chip_selects to "11"
set Output_disable to "k"
end vector
vector Chip_select_2_false
drive Data
set Address to "kkkkkkkkkk"
set Write_enable_bar to "k"
set Chip_selects to "00"
set Output_disable to "k"
end vector
vector Read_enable
set Address to "kkkkkkkkkk"
set Write_enable_bar to "k"
set Chip_selects to "01"
set Output_disable to "0"
end vector
vector Address_0000000000
initialize to Disable
set Address to "0000000000"
end vector
vector Address_0000000001
initialize to Disable
set Address to "0000000001"
end vector
vector Address_0000000011
initialize to Disable
set Address to "0000000011"
end vector
vector Address_0000000111
initialize to Disable
set Address to "0000000111"
end vector
vector Address_0000001111
initialize to Disable
set Address to "0000001111"
end vector
vector Address_0000011111
initialize to Disable
set Address to "0000011111"
end vector
vector Address_0000111111
initialize to Disable
set Address to "0000111111"
end vector
vector Address_0001111111
initialize to Disable
set Address to "0001111111"
end vector
vector Address_0011111111
initialize to Disable
set Address to "0011111111"
end vector
vector Address_0111111111
initialize to Disable
set Address to "0111111111"
end vector
vector Address_1111111111
initialize to Disable
set Address to "1111111111"
end vector
vector Data_write_0000
initialize to Write_enable
drive Data
set Data to "0000"
end vector
vector Data_write_0001
initialize to Write_enable
drive Data
set Data to "0001"
end vector
vector Data_write_0011
initialize to Write_enable
drive Data
set Data to "0011"
end vector
vector Data_write_0111
initialize to Write_enable
drive Data
set Data to "0111"
end vector
vector Data_write_1111
initialize to Write_enable
drive Data
set Data to "1111"
end vector
vector Data_write_1110
initialize to Write_enable
drive Data
set Data to "1110"
end vector
vector Data_write_1100
initialize to Write_enable
drive Data
set Data to "1100"
end vector
vector Data_write_1000
initialize to Write_enable
drive Data
set Data to "1000"
end vector
vector Data_write_1010
initialize to Write_enable
drive Data
set Data to "1010"
end vector
vector Data_write_0101
initialize to Write_enable
drive Data
set Data to "0101"
end vector
vector Data_write_0010
initialize to Write_enable
drive Data
set Data to "0010"
end vector
vector Data_write_1111_CS_false
drive Data
set Address to "kkkkkkkkkk"
set Write_enable_bar to "k"
set Chip_selects to "kk"
set Output_disable to "k"
set Data to "1111"
end vector
vector Data_read_0000
initialize to Read_enable
receive Data
set Data to "0000"
end vector
vector Data_read_0001
initialize to Read_enable
receive Data
set Data to "0001"
end vector
vector Data_read_0011
initialize to Read_enable
receive Data
set Data to "0011"
end vector
vector Data_read_0111
initialize to Read_enable
receive Data
set Data to "0111"
end vector
vector Data_read_1111
initialize to Read_enable
receive Data
set Data to "1111"
end vector
vector Data_read_1110
initialize to Read_enable
receive Data
set Data to "1110"
end vector
vector Data_read_1100
initialize to Read_enable
receive Data
set Data to "1100"
end vector
vector Data_read_1000
initialize to Read_enable
receive Data
set Data to "1000"
end vector
vector Data_read_1010
initialize to Read_enable
receive Data
set Data to "1010"
end vector
vector Data_read_0101
initialize to Read_enable
receive Data
set Data to "0101"
end vector
vector Data_read_0010
initialize to Read_enable
receive Data
set Data to "0010"
end vector
!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.
vector WEb_hi_D0
drive Data_D0
set Address to "kkkkkkkkkk"
set Data_D0 to "k"
set Write_enable_bar to "1"
set Chip_selects to "10"
set Output_disable to "k"
end vector
vector WEb_hi_D1
drive Data_D1
set Address to "kkkkkkkkkk"
set Data_D1 to "k"
set Write_enable_bar to "1"
set Chip_selects to "10"
set Output_disable to "k"
end vector
vector WEb_hi_D2
drive Data_D2
set Address to "kkkkkkkkkk"
set Data_D2 to "k"
set Write_enable_bar to "1"
set Chip_selects to "10"
set Output_disable to "k"
end vector
vector WEb_hi_D3
drive Data_D3
set Address to "kkkkkkkkkk"
set Data_D3 to "k"
set Write_enable_bar to "1"
set Chip_selects to "10"
set Output_disable to "k"
end vector
vector Data_write_D0_0
initialize to Write_enable
drive Data_D0
set Data_D0 to "0"
end vector
vector Data_write_D0_1
initialize to Write_enable
drive Data_D0
set Data_D0 to "1"
end vector
vector Data_write_D1_0
initialize to Write_enable
drive Data_D1
set Data_D1 to "0"
end vector
vector Data_write_D1_1
initialize to Write_enable
drive Data_D1
set Data_D1 to "1"
end vector
vector Data_write_D2_0
initialize to Write_enable
drive Data_D2
set Data_D2 to "0"
end vector
vector Data_write_D2_1
initialize to Write_enable
drive Data_D2
set Data_D2 to "1"
end vector
vector Data_write_D3_0
initialize to Write_enable
drive Data_D3
set Data_D3 to "0"
end vector
vector Data_write_D3_1
initialize to Write_enable
drive Data_D3
set Data_D3 to "1"
end vector
vector Data_read_D0_0
initialize to Read_enable
receive Data_D0
set Data_D0 to "0"
end vector
vector Data_read_D0_1
initialize to Read_enable
receive Data_D0
set Data_D0 to "1"
end vector
vector Data_read_D1_0
initialize to Read_enable
receive Data_D1
set Data_D1 to "0"
end vector
vector Data_read_D1_1
initialize to Read_enable
receive Data_D1
set Data_D1 to "1"
end vector
vector Data_read_D2_0
initialize to Read_enable
receive Data_D2
set Data_D2 to "0"
end vector
vector Data_read_D2_1
initialize to Read_enable
receive Data_D2
set Data_D2 to "1"
end vector
vector Data_read_D3_0
initialize to Read_enable
receive Data_D3
set Data_D3 to "0"
end vector
vector Data_read_D3_1
initialize to Read_enable
receive Data_D3
set Data_D3 to "1"
end vector
!***************************************************************
!***************************************************************
sub Write_data (Address, Data)
execute Address
execute Data
execute Write_enable_false
end sub
sub Read_data (Address, Data)
execute Address
execute Data
execute Disable
end sub
!AT The following subroutines have been added for a minimum pins test.
!AT Vectors in the subroutine "Write_data" reference the entire data bus.
!AT Therefore this subroutine was copied and modified to reference only
!AT a single pin of the data bus. The subroutine "Read_data" did not
!AT require any modification as all references to the data bus are made
!AT via a passed parameter (Data). This reference can be modified in the
!AT call statement.
sub Write_data_Dx (Address, Data_Dx, WEb_hi_Dx)
execute Address
execute Data_Dx
execute WEb_hi_Dx
end sub
!***************************************************************
!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.
unit "awaretest D0 Test"
call Write_data_Dx (Address_0000000000, Data_write_D0_0, WEb_hi_D0)
call Read_data (Address_0000000000, Data_read_D0_0)
call Write_data_Dx (Address_0000000000, Data_write_D0_1, WEb_hi_D0)
call Read_data (Address_0000000000, Data_read_D0_1)
end unit
unit "awaretest D1 Test"
call Write_data_Dx (Address_0000000000, Data_write_D1_0, WEb_hi_D1)
call Read_data (Address_0000000000, Data_read_D1_0)
call Write_data_Dx (Address_0000000000, Data_write_D1_1, WEb_hi_D1)
call Read_data (Address_0000000000, Data_read_D1_1)
end unit
unit "awaretest D2 Test"
call Write_data_Dx (Address_0000000000, Data_write_D2_0, WEb_hi_D2)
call Read_data (Address_0000000000, Data_read_D2_0)
call Write_data_Dx (Address_0000000000, Data_write_D2_1, WEb_hi_D2)
call Read_data (Address_0000000000, Data_read_D2_1)
end unit
unit "awaretest D3 Test"
call Write_data_Dx (Address_0000000000, Data_write_D3_0, WEb_hi_D3)
call Read_data (Address_0000000000, Data_read_D3_0)
call Write_data_Dx (Address_0000000000, Data_write_D3_1, WEb_hi_D3)
call Read_data (Address_0000000000, Data_read_D3_1)
end unit
unit "RAM test"
call Write_data (Address_0000000000, Data_write_0000)
call Write_data (Address_0000000001, Data_write_0001)
call Write_data (Address_0000000011, Data_write_0011)
call Write_data (Address_0000000111, Data_write_0111)
call Write_data (Address_0000001111, Data_write_1111)
call Write_data (Address_0000011111, Data_write_1110)
call Write_data (Address_0000111111, Data_write_1100)
call Write_data (Address_0001111111, Data_write_1000)
call Write_data (Address_0011111111, Data_write_1010)
call Write_data (Address_0111111111, Data_write_0101)
call Write_data (Address_1111111111, Data_write_0010)
call Read_data (Address_0000000000, Data_read_0000)
call Read_data (Address_0000000001, Data_read_0001)
call Read_data (Address_0000000011, Data_read_0011)
call Read_data (Address_0000000111, Data_read_0111)
call Read_data (Address_0000001111, Data_read_1111)
call Read_data (Address_0000011111, Data_read_1110)
call Read_data (Address_0000111111, Data_read_1100)
call Read_data (Address_0001111111, Data_read_1000)
call Read_data (Address_0011111111, Data_read_1010)
call Read_data (Address_0111111111, Data_read_0101)
call Read_data (Address_1111111111, Data_read_0010)
end unit
unit "Test Write_enable_1_false"
call Write_data (Address_0000000000, Data_write_0000)
execute Address_0000000000
execute Chip_select_1_false
execute Data_write_1111_CS_false
execute Write_enable_false
call Read_data (Address_0000000000, Data_read_0000)
end unit
unit "Test Write_enable_2_false"
call Write_data (Address_0000000000, Data_write_0000)
execute Address_0000000000
execute Chip_select_2_false
execute Data_write_1111_CS_false
execute Write_enable_false
call Read_data (Address_0000000000, Data_read_0000)
end unit
! End of test