!!!!    6    0    1  986756910  Ve721                                         

! Device           : 1220y
! Function         : 16K Nonvolatile SRAM
! revision         : B.01.00
! safeguard        : standard_cmos
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

sequential

assign  VCC                to pins           24
assign  GND                to pins           12

assign  Address_bus        to pins           19,22,23,1,2,3,4,5,6,7,8
assign  Data_bus           to pins           17,16,15,14,13,11,10,9
assign  Data_D0            to pins   9    !AT Added for minimum pin test.
assign  Data_D1            to pins   10   !AT Added for minimum pin test.
assign  Data_D2            to pins   11   !AT Added for minimum pin test.
assign  Data_D3            to pins   13   !AT Added for minimum pin test.
assign  Data_D4            to pins   14   !AT Added for minimum pin test.
assign  Data_D5            to pins   15   !AT Added for minimum pin test.
assign  Data_D6            to pins   16   !AT Added for minimum pin test.
assign  Data_D7            to pins   17   !AT Added for minimum pin test.

assign  CE_bar             to pins           18
assign  OE_bar             to pins           20
assign  WE_bar             to pins           21
assign  Disable_pins       to pins           18,21

family       TTL

power        VCC,GND

inputs       Address_bus, CE_bar, OE_bar, WE_bar

bidirectional       Data_bus
bidirectional  Data_D0, Data_D1, Data_D2, Data_D3 !AT Added for min. pin test.
bidirectional  Data_D4, Data_D5, Data_D6, Data_D7 !AT Added for min. pin test.

when     CE_bar         is "1"   inactive Data_bus
when     OE_bar         is "1"   inactive Data_bus
when     WE_bar         is "1"   outputs  Data_bus
when     WE_bar         is "0"   inputs   Data_bus

disable      Data_bus   with   Disable_pins  to    "00"
!*****************************************************************************
!*****************************************************************************

vector       Initialize
     set     CE_bar       to         "0"
     set     OE_bar       to         "0"
     set     WE_bar       to         "1"
     set     Address_bus  to         "00000000000"
end vector

vector       Keep_inputs
     set     CE_bar       to         "k"
     set     OE_bar       to         "k"
     set     WE_bar       to         "k"
     set     Address_bus  to         "kkkkkkkkkkk"
end vector

vector       Write_enable
     initialize to Keep_inputs
     set     WE_bar       to         "0"
end vector

vector       CE_bar_hi
     initialize to Keep_inputs
     set     CE_bar       to         "1"
end vector

vector       OE_bar_hi
     initialize to Keep_inputs
     set     OE_bar       to         "1"
end vector

vector       Address_00000000000
     initialize to Keep_inputs
     set     Address_bus  to         "00000000000"
end vector

vector       Address_00000000001
     initialize to Keep_inputs
     set     Address_bus  to         "00000000001"
end vector

vector       Address_00000000011
     initialize to Keep_inputs
     set     Address_bus  to         "00000000011"
end vector

vector       Address_00000000111
     initialize to Keep_inputs
     set     Address_bus  to         "00000000111"
end vector

vector       Address_00000001111
     initialize to Keep_inputs
     set     Address_bus  to         "00000001111"
end vector

vector       Address_00000011111
     initialize to Keep_inputs
     set     Address_bus  to         "00000011111"
end vector

vector       Address_00000111111
     initialize to Keep_inputs
     set     Address_bus  to         "00000111111"
end vector

vector       Address_00001111111
     initialize to Keep_inputs
     set     Address_bus  to         "00001111111"
end vector

vector       Address_00011111111
     initialize to Keep_inputs
     set     Address_bus  to         "00011111111"
end vector

vector       Address_00111111111
     initialize to Keep_inputs
     set     Address_bus  to         "00111111111"
end vector

vector       Address_01111111111
     initialize to Keep_inputs
     set     Address_bus  to         "01111111111"
end vector

vector       Address_11111111111
     initialize to Keep_inputs
     set     Address_bus  to         "11111111111"
end vector

vector       End_Write_cycle
     initialize to Keep_inputs
     drive Data_bus
     set     WE_bar       to         "1"
     set     Data_bus     to         "kkkkkkkk"
end vector

vector       Data_In_00000000
     initialize to Keep_inputs
     drive   Data_bus
     set     Data_bus     to         "00000000"
end vector

vector       Data_In_00000001
     initialize to Keep_inputs
     drive   Data_bus
     set     Data_bus     to         "00000001"
end vector

vector       Data_In_00000011
     initialize to Keep_inputs
     drive   Data_bus
     set     Data_bus     to         "00000011"
end vector

vector       Data_In_00000111
     initialize to Keep_inputs
     drive   Data_bus
     set     Data_bus     to         "00000111"
end vector

vector       Data_In_00001111
     initialize to Keep_inputs
     drive   Data_bus
     set     Data_bus     to         "00001111"
end vector


vector       Data_In_00011111
     initialize to Keep_inputs
     drive   Data_bus
     set     Data_bus     to         "00011111"
end vector

vector       Data_In_00111111
     initialize to Keep_inputs
     drive   Data_bus
     set     Data_bus     to         "00111111"
end vector

vector       Data_In_01111111
     initialize to Keep_inputs
     drive   Data_bus
     set     Data_bus     to         "01111111"
end vector

vector       Data_In_11111111
     initialize to Keep_inputs
     drive   Data_bus
     set     Data_bus     to         "11111111"
end vector

vector       Data_In_11111110
     initialize to Keep_inputs
     drive   Data_bus
     set     Data_bus     to         "11111110"
end vector

vector       Data_In_11111100
     initialize to Keep_inputs
     drive   Data_bus
     set     Data_bus     to         "11111100"
end vector

vector       Data_In_11111000
     initialize to Keep_inputs
     drive   Data_bus
     set     Data_bus     to         "11111000"
end vector

vector       Data_In_01010101
     initialize to Keep_inputs
     drive   Data_bus
     set     Data_bus     to         "01010101"
end vector

vector       Data_In_10101010
     initialize to Keep_inputs
     drive   Data_bus
     set     Data_bus     to         "10101010"
end vector

vector       Data_Out_00000000
     initialize to Keep_inputs
     receive Data_bus
     set     Data_bus     to         "00000000"
end vector

vector       Data_Out_00000001
     initialize to Keep_inputs
     receive Data_bus
     set     Data_bus     to         "00000001"
end vector

vector       Data_Out_00000011
     initialize to Keep_inputs
     receive Data_bus
     set     Data_bus     to         "00000011"
end vector

vector       Data_Out_00000111
     initialize to Keep_inputs
     receive Data_bus
     set     Data_bus     to         "00000111"
end vector

vector       Data_Out_00001111
     initialize to Keep_inputs
     receive Data_bus
     set     Data_bus     to         "00001111"
end vector

vector       Data_Out_00011111
     initialize to Keep_inputs
     receive Data_bus
     set     Data_bus     to         "00011111"
end vector

vector       Data_Out_00111111
     initialize to Keep_inputs
     receive Data_bus
     set     Data_bus     to         "00111111"
end vector

vector       Data_Out_01111111
     initialize to Keep_inputs
     receive Data_bus
     set     Data_bus     to         "01111111"
end vector

vector       Data_Out_11111111
     initialize to Keep_inputs
     receive Data_bus
     set     Data_bus     to         "11111111"
end vector

vector       Data_Out_11111110
     initialize to Keep_inputs
     receive Data_bus
     set     Data_bus     to         "11111110"
end vector

vector       Data_Out_11111100
     initialize to Keep_inputs
     receive Data_bus
     set     Data_bus     to         "11111100"
end vector

vector       Data_Out_11111000
     initialize to Keep_inputs
     receive Data_bus
     set     Data_bus     to         "11111000"
end vector

vector       Data_Out_01010101
     initialize to Keep_inputs
     receive Data_bus
     set     Data_bus     to         "01010101"
end vector

vector       Data_Out_xxxxxxx1
     initialize to Keep_inputs
     receive Data_bus
     set     Data_bus     to         "xxxxxxx1"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector       WEb_hi_D0
     initialize to Keep_inputs
     drive Data_D0
     set     WE_bar       to         "1"
     set     Data_D0      to         "k"
end vector

vector       WEb_hi_D1
     initialize to Keep_inputs
     drive Data_D1
     set     WE_bar       to         "1"
     set     Data_D1      to         "k"
end vector

vector       WEb_hi_D2
     initialize to Keep_inputs
     drive Data_D2
     set     WE_bar       to         "1"
     set     Data_D2      to         "k"
end vector

vector       WEb_hi_D3
     initialize to Keep_inputs
     drive Data_D3
     set     WE_bar       to         "1"
     set     Data_D3      to         "k"
end vector

vector       WEb_hi_D4
     initialize to Keep_inputs
     drive Data_D4
     set     WE_bar       to         "1"
     set     Data_D4      to         "k"
end vector

vector       WEb_hi_D5
     initialize to Keep_inputs
     drive Data_D5
     set     WE_bar       to         "1"
     set     Data_D5      to         "k"
end vector

vector       WEb_hi_D6
     initialize to Keep_inputs
     drive Data_D6
     set     WE_bar       to         "1"
     set     Data_D6      to         "k"
end vector

vector       WEb_hi_D7
     initialize to Keep_inputs
     drive Data_D7
     set     WE_bar       to         "1"
     set     Data_D7      to         "k"
end vector

vector       Data_In_D0_0
     initialize to Keep_inputs
     drive   Data_D0
     set     Data_D0      to         "0"
end vector

vector       Data_In_D0_1
     initialize to Keep_inputs
     drive   Data_D0
     set     Data_D0      to         "1"
end vector

vector       Data_In_D1_0
     initialize to Keep_inputs
     drive   Data_D1
     set     Data_D1      to         "0"
end vector

vector       Data_In_D1_1
     initialize to Keep_inputs
     drive   Data_D1
     set     Data_D1      to         "1"
end vector

vector       Data_In_D2_0
     initialize to Keep_inputs
     drive   Data_D2
     set     Data_D2      to         "0"
end vector

vector       Data_In_D2_1
     initialize to Keep_inputs
     drive   Data_D2
     set     Data_D2      to         "1"
end vector

vector       Data_In_D3_0
     initialize to Keep_inputs
     drive   Data_D3
     set     Data_D3      to         "0"
end vector

vector       Data_In_D3_1
     initialize to Keep_inputs
     drive   Data_D3
     set     Data_D3      to         "1"
end vector

vector       Data_In_D4_0
     initialize to Keep_inputs
     drive   Data_D4
     set     Data_D4      to         "0"
end vector

vector       Data_In_D4_1
     initialize to Keep_inputs
     drive   Data_D4
     set     Data_D4      to         "1"
end vector

vector       Data_In_D5_0
     initialize to Keep_inputs
     drive   Data_D5
     set     Data_D5      to         "0"
end vector

vector       Data_In_D5_1
     initialize to Keep_inputs
     drive   Data_D5
     set     Data_D5      to         "1"
end vector

vector       Data_In_D6_0
     initialize to Keep_inputs
     drive   Data_D6
     set     Data_D6      to         "0"
end vector

vector       Data_In_D6_1
     initialize to Keep_inputs
     drive   Data_D6
     set     Data_D6      to         "1"
end vector

vector       Data_In_D7_0
     initialize to Keep_inputs
     drive   Data_D7
     set     Data_D7      to         "0"
end vector

vector       Data_In_D7_1
     initialize to Keep_inputs
     drive   Data_D7
     set     Data_D7      to         "1"
end vector

vector       Data_Out_D0_0
     initialize to Keep_inputs
     receive Data_D0
     set     Data_D0      to         "0"
end vector

vector       Data_Out_D0_1
     initialize to Keep_inputs
     receive Data_D0
     set     Data_D0      to         "1"
end vector

vector       Data_Out_D1_0
     initialize to Keep_inputs
     receive Data_D1
     set     Data_D1      to         "0"
end vector

vector       Data_Out_D1_1
     initialize to Keep_inputs
     receive Data_D1
     set     Data_D1      to         "1"
end vector

vector       Data_Out_D2_0
     initialize to Keep_inputs
     receive Data_D2
     set     Data_D2      to         "0"
end vector

vector       Data_Out_D2_1
     initialize to Keep_inputs
     receive Data_D2
     set     Data_D2      to         "1"
end vector

vector       Data_Out_D3_0
     initialize to Keep_inputs
     receive Data_D3
     set     Data_D3      to         "0"
end vector

vector       Data_Out_D3_1
     initialize to Keep_inputs
     receive Data_D3
     set     Data_D3      to         "1"
end vector

vector       Data_Out_D4_0
     initialize to Keep_inputs
     receive Data_D4
     set     Data_D4      to         "0"
end vector

vector       Data_Out_D4_1
     initialize to Keep_inputs
     receive Data_D4
     set     Data_D4      to         "1"
end vector

vector       Data_Out_D5_0
     initialize to Keep_inputs
     receive Data_D5
     set     Data_D5      to         "0"
end vector

vector       Data_Out_D5_1
     initialize to Keep_inputs
     receive Data_D5
     set     Data_D5      to         "1"
end vector

vector       Data_Out_D6_0
     initialize to Keep_inputs
     receive Data_D6
     set     Data_D6      to         "0"
end vector

vector       Data_Out_D6_1
     initialize to Keep_inputs
     receive Data_D6
     set     Data_D6      to         "1"
end vector

vector       Data_Out_D7_0
     initialize to Keep_inputs
     receive Data_D7
     set     Data_D7      to         "0"
end vector

vector       Data_Out_D7_1
     initialize to Keep_inputs
     receive Data_D7
     set     Data_D7      to         "1"
end vector

!*****************************************************************************
!*****************************************************************************

sub  Write_Data (Address,Data)
      execute              Address
      execute              Write_enable
      execute              Data
      execute              End_Write_cycle
end sub

sub  Read_Data (Address,Data)
      execute              Address
      execute              Data
end sub

!AT The following subroutines have been added for a minimum pins test.
!AT Vectors in the subroutine "Write_data" reference the entire data bus.
!AT Therefore this subroutine was copied and modified to reference only
!AT a single pin of the data bus. The subroutine "Read_data" did not
!AT require any modification as all references to the data bus are made
!AT via a passed parameter (Data). This reference can be modified in the
!AT call statement.

sub  Write_data_Dx (Address, Data_Dx, WEb_hi_Dx)
      execute              Address
      execute              Write_enable
      execute              Data_Dx
      execute              WEb_hi_Dx
end sub

!*****************************************************************************
!*****************************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit   "awaretest D0 Test"

      execute   Initialize

      call      Write_Data_Dx (Address_00000000000, Data_In_D0_0, WEb_hi_D0)
      call      Read_Data (Address_00000000000, Data_Out_D0_0)

      call      Write_Data_Dx (Address_00000000000, Data_In_D0_1, WEb_hi_D0)
      call      Read_Data (Address_00000000000, Data_Out_D0_1)

end unit

unit   "awaretest D1 Test"

      execute   Initialize

      call      Write_Data_Dx (Address_00000000000, Data_In_D1_0, WEb_hi_D1)
      call      Read_Data (Address_00000000000, Data_Out_D1_0)

      call      Write_Data_Dx (Address_00000000000, Data_In_D1_1, WEb_hi_D1)
      call      Read_Data (Address_00000000000, Data_Out_D1_1)

end unit

unit   "awaretest D2 Test"

      execute   Initialize

      call      Write_Data_Dx (Address_00000000000, Data_In_D2_0, WEb_hi_D2)
      call      Read_Data (Address_00000000000, Data_Out_D2_0)

      call      Write_Data_Dx (Address_00000000000, Data_In_D2_1, WEb_hi_D2)
      call      Read_Data (Address_00000000000, Data_Out_D2_1)

end unit

unit   "awaretest D3 Test"

      execute   Initialize

      call      Write_Data_Dx (Address_00000000000, Data_In_D3_0, WEb_hi_D3)
      call      Read_Data (Address_00000000000, Data_Out_D3_0)

      call      Write_Data_Dx (Address_00000000000, Data_In_D3_1, WEb_hi_D3)
      call      Read_Data (Address_00000000000, Data_Out_D3_1)

end unit

unit   "awaretest D4 Test"

      execute   Initialize

      call      Write_Data_Dx (Address_00000000000, Data_In_D4_0, WEb_hi_D4)
      call      Read_Data (Address_00000000000, Data_Out_D4_0)

      call      Write_Data_Dx (Address_00000000000, Data_In_D4_1, WEb_hi_D4)
      call      Read_Data (Address_00000000000, Data_Out_D4_1)

end unit

unit   "awaretest D5 Test"

      execute   Initialize

      call      Write_Data_Dx (Address_00000000000, Data_In_D5_0, WEb_hi_D5)
      call      Read_Data (Address_00000000000, Data_Out_D5_0)

      call      Write_Data_Dx (Address_00000000000, Data_In_D5_1, WEb_hi_D5)
      call      Read_Data (Address_00000000000, Data_Out_D5_1)

end unit

unit   "awaretest D6 Test"

      execute   Initialize

      call      Write_Data_Dx (Address_00000000000, Data_In_D6_0, WEb_hi_D6)
      call      Read_Data (Address_00000000000, Data_Out_D6_0)

      call      Write_Data_Dx (Address_00000000000, Data_In_D6_1, WEb_hi_D6)
      call      Read_Data (Address_00000000000, Data_Out_D6_1)

end unit

unit   "awaretest D7 Test"

      execute   Initialize

      call      Write_Data_Dx (Address_00000000000, Data_In_D7_0, WEb_hi_D7)
      call      Read_Data (Address_00000000000, Data_Out_D7_0)

      call      Write_Data_Dx (Address_00000000000, Data_In_D7_1, WEb_hi_D7)
      call      Read_Data (Address_00000000000, Data_Out_D7_1)

end unit

unit    "Ram_Test"

      execute   Initialize

      call      Write_Data (Address_00000000000,Data_In_00000000)
      call      Write_Data (Address_00000000001,Data_In_00000001)
      call      Write_Data (Address_00000000011,Data_In_00000011)
      call      Write_Data (Address_00000000111,Data_In_00000111)
      call      Write_Data (Address_00000001111,Data_In_00001111)
      call      Write_Data (Address_00000011111,Data_In_00011111)
      call      Write_Data (Address_00000111111,Data_In_00111111)
      call      Write_Data (Address_00001111111,Data_In_01111111)
      call      Write_Data (Address_00011111111,Data_In_11111111)
      call      Write_Data (Address_00111111111,Data_In_11111110)
      call      Write_Data (Address_01111111111,Data_In_11111100)
      call      Write_Data (Address_11111111111,Data_In_11111000)

      call      Read_Data (Address_00000000000,Data_Out_00000000)
      call      Read_Data (Address_00000000001,Data_Out_00000001)
      call      Read_Data (Address_00000000011,Data_Out_00000011)
      call      Read_Data (Address_00000000111,Data_Out_00000111)
      call      Read_Data (Address_00000001111,Data_Out_00001111)
      call      Read_Data (Address_00000011111,Data_Out_00011111)
      call      Read_Data (Address_00000111111,Data_Out_00111111)
      call      Read_Data (Address_00001111111,Data_Out_01111111)
      call      Read_Data (Address_00011111111,Data_Out_11111111)
      call      Read_Data (Address_00111111111,Data_Out_11111110)
      call      Read_Data (Address_01111111111,Data_Out_11111100)
      call      Read_Data (Address_11111111111,Data_Out_11111000)
end unit

unit   "Test Chip Enable"
      execute   Initialize
      call      Write_Data (Address_00000111111,Data_In_01010101)
      execute   CE_bar_hi
      call      Write_Data (Address_00000111111,Data_In_10101010)
      execute   Initialize
      call      Read_Data  (Address_00000111111,Data_Out_01010101)
end unit

unit   "Test Output Enable"
      execute   Initialize
      call      Write_Data (Address_00000111111,Data_In_00000000)
      execute   Address_00000111111
      execute   OE_bar_hi
      execute   Data_out_xxxxxxx1
end unit

! End of Test